Effective Management of DRAM Bandwidth in Multicore Processors

Rafique, Nauman; Lim, Wontaek; Thottethodi, Mithuna

doi:10.1109/pact.2007.4336216

Cited by 80 publications

(77 citation statements)

References 30 publications

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“…QoS-aware memory controllers were proposed in various contexts including a packet memory environment [1] and multi-processor environments [2,3,4,5]. In [1], the proposed adaptive feedback mechanism dynamically adjusts allocated bandwidths to different classes based on latency violations.…”

Section: Related Workmentioning

confidence: 99%

“…In [1], the proposed adaptive feedback mechanism dynamically adjusts allocated bandwidths to different classes based on latency violations. In [2,3], a fair queueing method is employed to allocate bandwidth for different processor threads whereas in [4,5], priority scheduling is used to schedule threads based on their sensitivity to inter-thread interference, latency, or bandwidth.…”

Section: Related Workmentioning

confidence: 99%

“…However, the methods proposed for multi-processor environment in [2,3,4,5] are not adequate for the packet memory because data mapping on DRAM and data access patterns in the packet memory are different than those in the multi-processor environment. In [4,5], they provide high priority to the threads with latency sensitivity.…”

Section: Related Workmentioning

confidence: 99%

“…Step 5: We complete the bitmap by inserting the class number of the numerator by as many times as the remainder value, r. In above example, bmap [3] is set to 0 because r is one.…”

Section: Bitmap Generationmentioning

confidence: 99%

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Design of a bitmap-based QoS-aware memory controller for a packet memory

Yoon

Chung

et al. 2014

IEICE Electron. Express

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Abstract:A packet memory controller in routers accesses the packet memory according to the QoS requirements of packets. The previous QoS-aware controller using a feedback control loop degenerates into round robin scheduling under temporary overload and suffers from slow response. We propose a new packet memory controller that estimates input load accurately and rapidly and schedules different classes using a flexible bitmap scheduler. The results show that under temporary overload or rapidly changing input loads, it can successfully meet the latency requirements by showing only less than 2% difference from the requirement of the high priority class.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

“…Step 5: We complete the bitmap by inserting the class number of the numerator by as many times as the remainder value, r. In above example, bmap [3] is set to 0 because r is one.…”

Section: Bitmap Generationmentioning

confidence: 99%

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Design of a bitmap-based QoS-aware memory controller for a packet memory

Yoon

Chung

et al. 2014

IEICE Electron. Express

View full text Add to dashboard Cite

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“…One issue that varies considerably is the benchmark duration. Some papers define the benchmark duration by the number of instructions executed [4], [6], [9], [12], [16], though some are not clear whether that is instructions for each program, total instructions between all programs, when one program reaches a particular number of instructions, or some other condition. Other papers define the benchmark duration by the number of cycles executed [15], [17] or until the IPC converges [10].…”

Section: Introductionmentioning

confidence: 99%

Multi-program benchmark definition

Jacobvitz

Hilton

Sorin

2015

2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Abstract-Although definition of single-program benchmarks is relatively straight-forward-a benchmark is a program plus a specific input-definition of multi-program benchmarks is more complex. Each program may have a different runtime and they may have different interactions depending on how they align with each other. While prior work has focused on sampling multiprogram benchmarks, little attention has been paid to defining the benchmarks in their entirety.In this work, we propose a four-tuple that formally defines multi-program benchmarks in a well-defined way. We then examine how four different classes of benchmarks created by varying the elements of this tuple align with real-world use-cases. We evaluate the impact of these variations on real hardware, and see drastic variations in results between different benchmarks constructed from the same programs. Notable differences include significant speedups versus slowdowns (e.g., +57% vs -5% or +26% vs -18%), and large differences in magnitude even when the results are in the same direction (e.g., 67% versus 11%).

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Bandwidth Management in the Era of Bring Your Own Device

Chitanana

Govender

2015

E J Info Sys Dev Countries

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This research was undertaken to investigate the issue of how universities are managing utilisation of bandwidth in the face of increased Internet traffic in the era of ‘bring your own device’ (BYOD) and increased digital content. In particular, the research sought to find out about what universities in Zimbabwe were doing to ensure efficient utilisation of the limited bandwidth that is experience by most developing countries. A survey was carried out in a sample of five universities to catalogue their experiences. Results showed that most universities in the sample did not have an official Internet Access Policy to assist with bandwidth management. Technical solutions to successful provision of managed network bandwidth within a university involve the application of many network hardware tools, encompassing a number of different techniques, which are often expensive and out of reach of universities. Fortunately a cost‐effective solution exists for all universities, which can be deployed regardless of the campus’ existing network configuration or installed devices. The authors recommend that using quality of service and bandwidth management policies will enable network administrators to control network traffic flow so that appropriate users and applications get priority during the allocation of network resources. Also, universities must contain in their information technology policies a meaningful Internet Access Policy, which will help universities to develop and refine bandwidth access and usage and allow easy access to network resources.

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Effective Management of DRAM Bandwidth in Multicore Processors

Abstract: Abstract

Cited by 80 publications

References 30 publications

Design of a bitmap-based QoS-aware memory controller for a packet memory

Design of a bitmap-based QoS-aware memory controller for a packet memory

Multi-program benchmark definition

Bandwidth Management in the Era of Bring Your Own Device

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