Effective Robustness Analysis Using Bounded Model Checking Techniques

Fey, Görschwin; Sülflow, André; Frehse, Stefan; Drechsler, Rolf

doi:10.1109/tcad.2011.2120950

Cited by 25 publications

(8 citation statements)

References 42 publications

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“…Identification of architectural Validation of error-detection Correctness of locked logic; Proof-carrying validation covert channels [31] properties [32] De-obfuscation attacks [33] hardware […”

Section: Functionalmentioning

confidence: 99%

Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA

Knechtel,

Kavun,

Regazzoni

et al. 2020

Preprint

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Section: Functionalmentioning

confidence: 99%

Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA

Knechtel,

Kavun,

Regazzoni

et al. 2020

Preprint

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“…However, a complete proof then requires exhaustive simulation of all faults and all input patterns. To avoid this, more recent approaches apply BDD-based or SAT-based analysis as well as SAT-based ATPG [15,[21][22][23]. Subsection 4.1 explains how fault secureness and self-testability can be checked with SAT-based ATPG while Subsection 4.2 focuses on strong fault secureness.…”

Section: Analyzing Fault Tolerancementioning

confidence: 99%

“…However, standard synthesis procedures are not tailored to the specific requirements of self-checking logic. On the one hand, they may violate design constraints, such that fault tolerance properties must be verified after synthesis [15,22,23]. On the other hand, they are not able to take advantage of the specific optimization potential for code generators, prediction logic and checkers [9].…”

Section: Introductionmentioning

confidence: 99%

SAT-based ATPG beyond stuck-at fault testing

Hellebrand¹,

Wunderlich²

2014

It - Information Technology

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Abstract:To cope with the problems of technology scaling, a robust design has become desirable. Self-checking circuits combined with rollback or repair strategies can provide a low cost solution for many applications. However, standard synthesis procedures may violate design constraints or lead to sub-optimal designs. The SATbased strategies for the verification and synthesis of selfchecking circuits presented in this paper can provide efficient solutions.

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“…Another application area of verification tools is the analysis of transient faults [4]- [6]. For analyzing transient faults, it is important to know for how many time cycles the fault may affect the output of the circuit at the maximum.…”

Section: Introductionmentioning

confidence: 99%

Latency Analysis for Sequential Circuits

Finder¹,

Sülflow²,

Fey

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Verifying correctness is a major bottleneck in today's circuit and system design. Verification includes the tasks of error detection, error localization, and error correction in an implemented design, as well as the analysis and avoidance of transient faults. For all those tasks, knowing when an assignment to signals becomes observable at the outputs and for how long it influences the system is important. In this letter, we propose a minimal and maximal latency measure for sequential circuits. This measure explains how long a circuit's state and outputs depend on input stimuli. Exact and heuristic algorithms are discussed to determine the measure. We evaluate the algorithms on state-of-the-art designs. Experimental results show how the measure provides insight into the behavior of circuit designs.

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Effective Robustness Analysis Using Bounded Model Checking Techniques

Cited by 25 publications

References 42 publications

Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA

Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA

SAT-based ATPG beyond stuck-at fault testing

Latency Analysis for Sequential Circuits

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