Effective scan chain failure analysis method

Auvray, Etienne; Armagnat, Paul; Saury, Luc; Jothi, M. Arul; Brügel, Michael

doi:10.1016/j.microrel.2017.07.024

Cited by 10 publications

(3 citation statements)

References 11 publications

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“…In the scan chain process, there are potential failures caused among others by stuck-atfaults and timing faults among others is excessive test power consumption, to overcome this some authors propose scan-chain architecture to reduce test power consumption such as [15]. An indication of the failure of the scan chain is a very low or zero yield, even today where modern chips are based on nanometer technology, some researchers propose a low cost method for stuck-at-fault problems where the method of diagnosing the problem is claimed to be effective, low complexity, solution suitable as Dounavi et al proposed [16], the above hardware-assisted diagnostic method is claimed to be better than the simulation diagnostic method, but due to the considerable overhead, the method is said to be not accepted in practical designs, therefore Ahlawat et al proposed the hardware-assisted method following the previous method and the proposed design has less gate overhead in terms of area and performance [17]. In today's world where the chip size is in nanometers, scan-chain faults are analyzed using Neural Networks such as [18] to produce a better diagnosis.…”

Section: Modification Process By Adding a Scan-chainmentioning

confidence: 99%

Fault Coverage Testing on the ISCAS’89 S1423 Sequential Circuit using Scan Based Design and Synopsis Tetramax

Suteddy,

Adiwilaga,

Atmanto

2022

COELITE

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We tested the ISCAS'89 S1423 series with a scan design method, both non-scan, full-scan, and partial-scan, but for the partial-scan, the method we propose uses a structured random approach. The purpose of this study is to determine the evaluation and performance with the best computational time with the proposed method to produce high fault coverage results. Testing the ISCAS'89 S1423 circuit in the form of verilog was carried out using tetramax synopsis, the partial-scan test requires a strategy in determining the flip flop to be used as a scannable flip flop, the test results using the full scan method produce 100% test coverage and fault coverage, but this method provides gate overhead loss of 24.06% and slower chip performance. To reduce the gate overhead loss, a partial-scan method will be applied with the approach of choosing from 74 DFF which will be used as scannable flip flops, the test with the best results we did through the 37 DFF approach with the highest input obtained test coverage of 98.17% and fault coverage 96.76% with 171.11 CPU Time with gate overhead reduced by 12.03%. The next approach with the best results with the approach of 50 DFF highest output plus DFF which is not self-loop obtained test coverage of 99.24% and fault coverage of 98.47% with gate overhead successfully reduced by 16.26% with CPU Time 43.39.

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Section: Modification Process By Adding a Scan-chainmentioning

confidence: 99%

Fault Coverage Testing on the ISCAS’89 S1423 Sequential Circuit using Scan Based Design and Synopsis Tetramax

Suteddy,

Adiwilaga,

Atmanto

2022

COELITE

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“…A faster and accurate failure analysis helps improve the design to reduce failure rates and thus aids yield improvements. Avalon, a tool by Synopsys as a failure analysis tool, helps the FA engineer in the fault localization process [11,12]. Avalon provides easy collaboration of product and design groups with FA labs, thus improving time to yield and market.…”

Section: Fabrication Centric Solutions For Process/product Ramp and Pmentioning

confidence: 99%

“…Avalon as a tool is an effective tool for fault localization. The tool also offers powerful debug capabilities for failure analysis at advanced technology nodes [12]. Figure 1 shows the two fault diagnosis techniques, including a technique for identifying the fault sites without physical failure analysis and a technique for identifying the fault sites efficiently by assessing the cause from the diagnosis results and selecting samples to be subjected to failure analysis [13].…”

Section: Introductionmentioning

confidence: 99%

Efficient Fault Localization and Failure Analysis Techniques for Improving IC Yield

Oberai

Yuan

2018

Electronics

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With the increase in the complexity of the semiconductor device processes and increase in the challenge to satisfy high market demands, enhancement in yield has become a crucial factor. Discovering and reacting to yield problems emerging at the end of the production line may cause unbearable yield loss leading to larger times to market. Thus, time and cost involved in fault isolation may be significantly shortened by effectively utilizing the fault diagnosis technology and supporting yield improvements. Hence for yield analysis, a highly integrated data network with software analysis tools have been established to reduce the fault analysis time. Synopsys Avalon, a product used for fault localization is described in this paper which aids in achieving better integrated circuit yields. This paper also illustrates various fault localization techniques for faster problem identification and discusses a few analytical tools like photon emission microscope and transmission emission microscope for faster determination of device failures.

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Light Emission Tracking and Measurements for Analog Circuits Fault Diagnosis in Automotive Applications

Melis

Simeu

Auvray³

et al. 2023

J Electron Test

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Effective scan chain failure analysis method

Cited by 10 publications

References 11 publications

Fault Coverage Testing on the ISCAS’89 S1423 Sequential Circuit using Scan Based Design and Synopsis Tetramax

Fault Coverage Testing on the ISCAS’89 S1423 Sequential Circuit using Scan Based Design and Synopsis Tetramax

Efficient Fault Localization and Failure Analysis Techniques for Improving IC Yield

Light Emission Tracking and Measurements for Analog Circuits Fault Diagnosis in Automotive Applications

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