Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated Circuits

Gunti, Nagendra Babu; Lingasubramanian, Karthikeyan

doi:10.1016/j.vlsi.2017.06.002

Cited by 12 publications

(9 citation statements)

References 22 publications

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“…The possibility of this kind of behaviour, along with the fact that Trojans are stealthy make it difficult to conjure effective Trojan detection schemes. To counter such situations, the current focus of researchers is to neutralize them apart from detecting the Trojans (Gunti and Lingasubramanian, 2017).…”

Section: Effect Of the Triggered Trojansmentioning

confidence: 99%

Peer Review #4 of "A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study (v0.2)"

2020

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Integrated circuits may be vulnerable to hardware Trojan attacks during its design or fabrication phases. This paper is a case study of the design of a Viterbi decoder and the effect of hardware Trojans on a coded communication system employing the Viterbi decoder. Design of a Viterbi decoder and possible hardware Trojan models for the same are proposed. An FPGA-based implementation of the decoder and the associated Trojan circuits have been discussed. The noise-added encoded input data stream is stored in the block RAM of the FPGA and the decoded data stream is monitored on the PC through an UART interface. The implementation results show that there is barely any change in the LUTs used (0.5%) and power dissipation (3%) due to the insertion of the proposed Trojan circuits, thus establishing the surreptitious nature of the Trojan. In spite of the fact that the Trojans cause negligible changes in the circuit parameters, there are significant changes in the bit error rate (BER) due to the presence of Trojans. In the absence of Trojans, BER drops down to zero for SNRs higher than 6 dB, but with the presence of Trojans, BER doesn't reduce to zero even at a very high SNRs. This is true even with the Trojan being activated only once during the entire duration of the transmission.

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Section: Effect Of the Triggered Trojansmentioning

confidence: 99%

Peer Review #4 of "A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study (v0.2)"

2020

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“…The possibility of this kind of behavior, along with the fact that Trojans are stealthy make it difficult to conjure effective Trojan detection schemes. To counter such situations, the current focus of researchers is to neutralize them apart from detecting the Trojans (Gunti & Lingasubramanian, 2017).…”

Section: Performance Degradationmentioning

confidence: 99%

A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study

Kakkara

Balasubramanian

Yamuna

et al. 2020

PeerJ Computer Science

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Integrated circuits may be vulnerable to hardware Trojan attacks during its design or fabrication phases. This article is a case study of the design of a Viterbi decoder and the effect of hardware Trojans on a coded communication system employing the Viterbi decoder. Design of a Viterbi decoder and possible hardware Trojan models for the same are proposed. An FPGA-based implementation of the decoder and the associated Trojan circuits have been discussed. The noise-added encoded input data stream is stored in the block RAM of the FPGA and the decoded data stream is monitored on the PC through an universal asynchronous receiver transmitter interface. The implementation results show that there is barely any change in the LUTs used (0.5%) and power dissipation (3%) due to the insertion of the proposed Trojan circuits, thus establishing the surreptitious nature of the Trojan. In spite of the fact that the Trojans cause negligible changes in the circuit parameters, there are significant changes in the bit error rate (BER) due to the presence of Trojans. In the absence of Trojans, BER drops down to zero for signal to noise rations (SNRs) higher than 6 dB, but with the presence of Trojans, BER doesn’t reduce to zero even at a very high SNRs. This is true even with the Trojan being activated only once during the entire duration of the transmission.

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“…The use of DMR and TMR to thwart HTs has been introduced in [3], [4], [5]. However, straightforward replication is not considered as an obstacle to insert an HT in these ICs.…”

Section: Introductionmentioning

confidence: 99%

Using Approximate Circuits Against Hardware Trojans

et al. 2023

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Hardware Trojans (HTs) are malicious alterations in Integrated Circuits (ICs) that pose an important threat to safety-critical systems. Many techniques based on logic testing or side-channel analysis have been proposed in the literature aiming at detecting such malicious modifications in fabricated ICs. The detection of HTs is becoming more challenging with the shrinking of the technology and the impact of process variations. Therefore there is a need to neutralize the effect of HTs when the typical detection mechanism fails. In this work, we propose to tackle the effect of HTs by leveraging fault-tolerant techniques like Triple Modular Redundancy (TMR). More specifically, we propose to use an approximate TMR in order to neutralize the effects of HTs while saving area and increasing the complexity of inserting HTs. The efficiency of the proposed approach has been evaluated by using the ISCAS'85 benchmarks and stealthy ad-hoc HTs.

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Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated Circuits

Cited by 12 publications

References 22 publications

Peer Review #4 of "A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study (v0.2)"

Peer Review #4 of "A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study (v0.2)"

A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study

Using Approximate Circuits Against Hardware Trojans

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