Effectively paralleling gallium nitride transistors for high current and high frequency applications

Abstract

Gallium nitride (GaN) based power devices are rapidly being adopted due to their ability to operate at frequencies and switching speeds beyond the capability of silicon (Si) power MOSFETs. In this paper, we will discuss paralleling high speed GaN transistors in applications requiring higher output current. This work will discuss the impact of in-circuit parasitics on performance and propose printed circuit board (PCB) layout methods to improve parallel performance of high speed GaN transistors. Four parallel half bridges in an optimized layout operated as a 48 V to 12 V, 480 W, 300 kHz, 40 A single phase buck converter achieving efficiencies above 96.5% from 35% to 100% load will be demonstrated. Also in this paper, we will discuss the latest eGaN ® FET developments including the fourth generation devices designed for higher current handling capability.978-1-4799-6735-3/15/$31.00 ©2015 IEEE

A Survey on Bidirectional DC/DC Power Converter Topologies for the Future Hybrid and All Electric Aircrafts

“…GaN MOSFETs outperform Si MOSFETs, in terms of figures of merit that relate devices on resistance with parasitic capacitances [37]. In other words, they feature less conduction and/or switching losses than their Si counterparts, so it is expected that their use might yield a certain efficiency improvement in the LV MOSFETs.…”

“…In order to estimate the impact of GaN technology in our particular DAB designs, we have considered a half bridge of four paralleled GaN switches. Layout parasitics were modelled following manufacturer design guidelines [37], and a loss model based on SPCICE simulations was obtained, as a function of bus voltage and inductive load current. Obtained results for nominal LVDC voltage are depicted in Figure 13.…”

Layout-Based Ultrafast Short-Circuit Protection Technique for Parallel-Connected GaN HEMTs

“…However, whenever the layout based sense method is adopted for GaN HEMTs, the layout parasitics should be minimized [9]. For parallel connected GaN HEMTs, these parasitics must not only be minimized to achieve the best performance but also need to be balanced to ensure proper parallel operation [18].…”

Investigations on Driver and Layout for Paralleled GaN HEMTs in Low Voltage Application

“…However, these parallel operation methods could not be directly applied in the GaN HEMTs parallel applications, because the GaN HEMTs have lower driving voltage and lower gate threshold voltage (V th ). There are many studies on high voltage GaN HEMTs in paralleled application, but few on low voltage GaN HEMTs [23]- [26]. In [23], a half-bridge double pulse circuit is demonstrated and the four paralleled GaN HEMTs (650V/60A) realized hard switching transition.…”

“…There are many studies on high voltage GaN HEMTs in paralleled application, but few on low voltage GaN HEMTs [23]- [26]. In [23], a half-bridge double pulse circuit is demonstrated and the four paralleled GaN HEMTs (650V/60A) realized hard switching transition. In [26], a buck converter with lowvoltage GaN HEMTs in parallel connection is prototyped.…”