Effects and prevention of source/drain ion implantation into the polysilicon in a BiCMOS technology

A method for improving the performance of a single polysilicon NPN transistor by using cumulafive/dual photoresist processing is presented. The photoresist from the polysilicon emitter layer patterning is preserved and over-coated in fhe subsequent extrinsic base implant masking layer. The n-fype emifter polysilicon is thus pmtected from counter-doping by the p-type extrinsic base implantation in a seIfaligned manner. Elecfrical consequences of applying this process, which include improved current gain and cutosfrequency, are reported.

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NPN transistor improvement by cumulative resist processing

Szendrei

Leibiger

Doyle

2004 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (IEEE Cat. No.04CH37530)

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Effects and prevention of source/drain ion implantation into the polysilicon in a BiCMOS technology

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References 7 publications

NPN transistor improvement by cumulative resist processing

NPN transistor improvement by cumulative resist processing

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