Effects of bias cooling on charge states in heterostructures embedding self-assembled quantum dots

Abstract

Carrier transfer behavior has been investigated in selectively doped InGaAs/AlGaAs heterojunctions, in which a layer of self-assembled InAs quantum dots is embedded in close vicinity to a two-dimensional electron gas ͑2DEG͒. We applied the bias-cooling technique to derive information on the electron exchange properties from the bias dependence of the capacitance-voltage ͑CV͒ spectroscopy. Noise is observed in the CV results at large reverse biases after sufficiently negative bias cooling. The noise is temperature sensitive and can be eliminated when raising the temperature to 130 K. In combination with the experimental results in the control sample, we find that the noise induced by the bias cooling is most likely associated with the hot-electron trapping and detrapping in DX centers in the selectively doped AlGaAs layer. The effect of light illumination on the CV results supports our speculation on the noise origin. Furthermore, the variation in the 2DEG carrier concentration and mobility with bias-cooling processes has been discussed, which provides a direct insight into the vertical charge-transfer mechanism among the quantum dot related electronic states, DX centers, and 2DEG channel.

Quantized rectification in a quantum dot nanojunction

“…Large fluctuations in the device characteristics as reported, e.g., for bias cooled devices were not found. 24 The current I versus V bias is shown in Fig. 3͑a͒ for V g = 0.7, 1.0, 1.3, 1.6, 1.9, and 2.2 V. For V g = 2.2 V, I is negative at small V bias and increases monotonically with increasing V bias .…”

Quantum Hall effect in graphene transferred by water-soluble transfer sheet and home-use laminator

“…The bias cooling is often used for III-V semiconductor heterostructures or quantum dots. 40,41) In our case, the sample was cooled from 300 to 1.5 K with applying V G = +40 V. At 300 K by applying V G , the Fermi level was increased and electrons were trapped by the trap states at higher energy than those at V G = 0 V. After the cooling, many of the trap states with electrons were frozen. Even when V G was decreased, these trap states would not release the electrons.…”

Engineering of electroplated materials for multilayer next generation graded bandgap solar cells

“…Capacitance-Voltage (C-V) technique has been well explored in the literature and utilised for the determination of diode electronic properties, in which parameters such as capacitance at zero bias (C o ) can be directly determined from the C-V curve while other parameters such as Fermi level (E F ) position with respect to both the conduction (E C ) and valence bands (E V ), built-in potential (V bi ), doping concentration of donors (N D ) or acceptors (N A ), barrier height Φ b , charge carrier mobility (µ⊥) and the depletion width at zero bias (W) [49] can be determined using Mott-Schottky plots. The Mott-Schottky plot is a graph of C -2 against V. For this report, the C-V technique was performed at 1 MHz due to the reduction in defect interference at high frequency [143], under dark condition due to noise caused by the high capture and emission of electrons at R&G centers [144] at room temperature.…”