Effects of cache coherency in multiprocessors

Dubois, Michel; Briggs, Fayé A.

doi:10.1145/1067649.801739

Cited by 12 publications

(13 citation statements)

References 8 publications

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“…Un répertoire centralisé consiste à maintenir dans un tableau partagé l'état courant des blocs mémoires répartis entre tous les processeurs (Censier et al, 1978;Dubois et al, 1982). Cette solution, largement utilisée dans les architectures à haute performance, engendre cependant un surcoût temporel important, pénalisant fortement les performances de l'architecture.…”

Section: Gestion De La Cohérenceunclassified

Les architectures parallèles sur puce. Synthèse des architectures multitâches pour les systèmes embarqués

Ventroux¹,

David²

2010

Techniques et sciences informatiques

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Les systèmes embarqués sont aujourd'hui omniprésents et nécessitent des puissances de calcul toujours plus importantes. Les dispositifs électroniques embarqués envahissent notre vie quotidienne et des milliers d'applications ou de fonctionnalités numériques nous accompagnent en permanence. Les architectures de calcul doivent alors être capables d'atteindre un très haut niveau de performance sous de fortes contraintes d'intégration et de consommation d'énergie. Une solution très efficace pour les systèmes embarqués consiste à multiplier le nombre de ressources de calcul sur une même puce. Ce sont les architectures multiprocesseurs. Elles permettent de traiter de multiples tâches en parallèle sur plusieurs ressources de calcul, voire de favoriser l'exécution concurrente de multiples applications. Cet article synthétise l'état de l'art des solutions existantes. ABSTRACT. Embedded systems are today pervasives and need more and more important computation efficiency. Embedded electronic devices overrun our daily life and million of applications and digital functions are permanently around us. In the future, we will see the utilization boom of these services, which will need very highly performing computing architectures under integration and energy consumption constraints. A solution that can be efficiently exploited in embedded systems consists in multiplying the number of computing resources on the same die. These are multiprocessor architectures. They offer the possibility to execute multiple tasks in parallel onto several computing resources and to eventually favour concurrent execution of multiple applications. This article is a survey on existing solutions.

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Section: Gestion De La Cohérenceunclassified

Les architectures parallèles sur puce. Synthèse des architectures multitâches pour les systèmes embarqués

Ventroux¹,

David²

2010

Techniques et sciences informatiques

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“…The system workload model consists of two memory reference streams, one to private blocks and another to shared blocks. Dubois and Briggs [ 1982] used an independent reference model (IRM) for shared-block accesses and a least recently used stack model (LRUSM) for private block accesses. An IRM for shared-block accesses is not adopted here since it does not capture any locality.…”

Section: Workload Modelmentioning

confidence: 99%

A Cache coherence protocol for MIN-based multiprocessors

1994

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In this paper we present a cache coherence protocol for multistage interconnection network (MIN)based multiprocessors with two distinct private caches: private-blocks caches (PCache) containing blocks private to a process and shared-blocks caches (SCache) containing data accessible by all processes. The architecture is extended by a coherence control bus connecting all shared-block cache controllers. Timing problems due to variable transit delays through the MIN are dealt with by introducing Transient states in the proposed cache coherence protocol. The impact of the coherence protocol on system performance is evaluated through a performance study of three phases. Assuming homogeneity of all nodes, a single-node queuing model (phase 3) is developed to analyze system performance. This model is solved for processor and coherence bus utilizations using the mean value analysis (MVA) technique with shared-blocks steady state probabilities (phase 1) and communication delays (phase 2) as input parameters. The performance of our system is compared to that of a system with an equivalent-sized unified cache and with a multiprocessor implementing a directory-based coherence protocol. System performance measures are verified through simulation.

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“…One approach is a "static coherence check," which avoids multiple copies of shared variables and allows only one copy of global variables. A second approach is "dynamic coherence check," in which multiplecopiesof global variables are allowed, but they are discarded when the global variables are modified [54]. A more systematic approach is proposed in [55], in which the compiler detects the variables that can cause a coherence problem and carefully allows multiple copies of them.…”

Section: ) Memory Allocationmentioning

confidence: 99%

Computational models and resource allocation for supercomputers

Mauney

Agrawal

Choe³

et al. 1989

Proc. IEEE

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Supercomputers are capable of providing tremendous computational power, but must be carefully programmed to take advantage of that power. There are several different architectures used in supercomputers, with differing computational models. These different models present a variety of resource allocation problems that must be solved. The computational needs of a program must be cast in terms of the computational model supported by the supercomputer, and this must be done in a way that makes effective use of the machine's resources. This is the resource allocation problem. The computational models of available supercomputers and the associated resource allocation techniques are surveyed. It is shown that many problems and solutions appear repeatedly in very different computing environments.

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Effects of cache coherency in multiprocessors

Cited by 12 publications

References 8 publications

Les architectures parallèles sur puce. Synthèse des architectures multitâches pour les systèmes embarqués

Les architectures parallèles sur puce. Synthèse des architectures multitâches pour les systèmes embarqués

A Cache coherence protocol for MIN-based multiprocessors

Computational models and resource allocation for supercomputers

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