Effects of CMP Process Conditions on Defect Generation in Low-k Materials

Abstract

The effects of chemical mechanical planarization ͑CMP͒ process parameters and consumables on the polish rate and defects generated in various low-k materials with k values ranging from 2.2 to 3.0 were studied in detail. The process consumables and conditions evaluated include slurry material ͑alumina and silica͒, pad type ͑soft and hard͒, polish pressure, and polish time. Atomic force microscopy ͑AFM͒ images and roughness numbers were used to evaluate the post-CMP defect generation under various process conditions and revealed nano/microscratches, pits, voids, and film delamination. For a given material, the removal rate increased with increasing pressure. The dependence of defects on pressure appeared highly driven by the slurry material, pad type, and low-k material properties. Defects increased with increasing pad hardness and decreasing k values. The increasing defects with decreasing k value can be attributed to the lower elastic modulus observed with low-k materials. Removal rates exhibited both a decrease and an increase in conjunction with polish time, depending on the type of low-k material used. AFM analysis showed an improvement in global surface roughness with increasing polish time; however, an increase in localized defects such as pits was also observed. Fourier transform infrared and X-ray photoelectron spectroscopy analyses showed no change in film chemistry under the conditions studied here.With advancements in ultralarge-scale integration, integrated microelectronic device dimensions are continually being scaled down. At present, manufacturers are running 0.11 m technology in their production lines, which increases the number of dies per wafer and reduces manufacturing costs. In addition, higher device speed requirements have forced the industry to include material changes in the device interconnection array. For example, in an attempt to reduce the resistance-capacitance time delay, manufacturers have moved toward a copper damascene process, with copper replacing aluminum and low-k dielectric materials replacing SiO 2 .Chemical mechanical planarization ͑CMP͒ is an important step in the copper damascene process. Copper deposited in the patterned dielectric trenches is planarized by CMP. The primary objective of the Cu-CMP process is to planarize and remove excess copper and the barrier layer. During this process, the underlying dielectric material is exposed. With industry shifts toward ultra low-k materials, very low k values can usually be achieved by using porous/organic materials, which also exhibit low hardness and modulus. However, these relatively weak materials cannot withstand the rigorous CMP process. Additionally, low-k films are less moisture resistant than conventional oxides produced by chemical vapor deposition ͑CVD͒; thus, extended exposure to CMP slurries and the environment affects their properties.Numerous low-k materials are being investigated. The compatibility of these materials with the CMP process is a significant factor in determining the appropriate low-k material to us...

Colloid aspects of chemical–mechanical planarization

“…For example, slurries used for planarizing Cu films contain H 2 O 2 as an oxidizer, an amino acid (such as glycine) acting as a chelating or complexing agent, an inhibitor to passivate the film and control the dissolution, a surfactant, a pH controlling agent, etc., as well as typically 50-200 nm sized abrasives [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16]. While silica and alumina particles are commonly used for polishing copper and tungsten, silica and ceria are used to polish SiO 2 , poly-Si, Si 3 N 4 and perhaps low-k films [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23]. Recently, composite abrasives in which core particles are coated or covered by a material of a different chemical composition, have also been investigated [24][25][26][27][28].…”

Potassium Oleate as a Dissolution and Corrosion Inhibitor during Chemical Mechanical Planarization of Chemical Vapor Deposited Co Films for Interconnect Applications

“…16 This can lead to device failure or create paths (See Figure 2) to the underneath barrier layers and the adjacent interlevel dielectric and, hence, should be avoided. In addition, Co structures must be polished at a sufficiently low (≤ 2 psi) down-pressure to avoid structural deformation of the underlying ultralow-k materials and to avoid erosion 17 ( Figure 1). Furthermore, during barrier polishing, galvanic corrosion 12,16,[18][19][20][21] can occur when electrochemically different materials are electrically connected and immersed in an electrolyte, as shown in Figure 2.…”

Editors' Choice—Efficiency of a CMP Pad at Removing Protective Material from Copper during CMP

“…The upper bound force estimate gave a penetration depth of the order of 1 nm for plastic deformation, which is of the same order as the roughness after copper CMP. 34,35 For lower concentrations of the abrasives, the experimentally evaluated removal efficiencies approximated well the analytical predictions for copper elastically deformed by the lower bound of the estimated force, regardless of the assumed pad surface topography parameters. This implies that the pad asperities supported by the abrasives were deformed enough to encapsulate the copper, such that the force applied to the embedded abrasive particles approached the lower bound of the estimate.…”