This study investigated the effects of tungsten (W) film morphology on the chemical mechanical polishing (CMP) of W. Chemical vapor deposited (CVD) W films with two distinctively different grain sizes were used for comparison. During polishing, W film thickness and optical reflectance, friction, and pad temperature were monitored in-situ. It was found that larger-grained W film took longer to pass the initial low removal rate stage. By correlating four different sensor signals, comparing friction dependency on film morphology, in slurry vs. DIW, it was concluded that W CMP comprises three main stages. First is the low rate initiation stage: grain is being partially planarized, reflectance increases, friction decreases. Second is the transition stage: rate is ramping, grain becomes fully planarized, optical reflectance reaches maximum, and friction becomes minimal followed by a significant rise caused by formation of tungsten oxide passivation layer on the planarized W surface. Third is the high and constant rate stage: passivation and removal occur in a repetitive cycle, friction is high and stable, optical reflectance changes as polishing reaches different film depths. In all three stages, pad temperature increases continuously as friction-induced heat dissipates, with the rate of temperature increase following that of friction magnitude. Metal CMP has enabled integrated circuit (IC) scaling as summarized in Table I. Depending on metal types and their different reactivity, different deposition methods are used. For example, aluminum (Al), a highly reactive metal, is deposited by high-temperature physical vapor deposition (PVD); whereas copper (Cu) as a noble metal is deposited by electrochemical plating (ECP) on top of a PVD Cu seed layer; W is deposited by CVD as its precursors and reaction by-product are in the gaseous phase. CVD cobalt is emerging as a replacement for Cu in back-end-of-line interconnects as it can fill much smaller line widths. Given their superior gap fill ability, CVD and atomic layer deposition (ALD) will become more common as IC scaling continues to 10 nm and beyond.CVD W and W CMP are widely used in IC manufacturing. W CMP was first introduced in 1995 as contact metal and enabled 0.35 μm technology yield and defect readiness.1 More recently, CVD W and W CMP enabled FinFET replacement metal gate (RMG) 2 when PVD Al could no longer fill in the small gate in the 3D structure. In addition to contact metal and gate metal in logic devices, W is widely used in memory, where 3D NAND involves many steps of CVD W and W CMP. CVD W grain size and crystalline orientation are dependent on many parameters, including the sub-layer films, ALD W nucleation, and CVD W deposition precursors and deposition temperature.3 For instance, CVD W is mostly dominated by alpha phase with (110) orientation >80% at 400• C, with some portion of beta phase (114) if CVD W temperature is higher.4 Different types of W applications have different sub-layers and deposition conditions. For CVD W used in contact, sub-layers in...