Effects of dislocations in silicon transistors with implanted bases

Bull, Charlotte; Ashburn, P.; Booker, G. R.; Nicholas, K. H.

doi:10.1016/0038-1101(77)90001-6

Cited by 39 publications

(5 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Seidel et a1 (1975b) have since reported similar effects. Damage correlates closely with both leakage currents and gains in deeper devices with implanted bases (Ashburn et al 1976b). Similar effects have been seen with implanted emitters (Ashburn et a1 1976a) but there are differences.…”

Section: 2 Reduction In Carrier Lifetimesupporting

confidence: 66%

Implantation damage in silicon devices

Nicholas¹

1977

J. Phys. D: Appl. Phys.

View full text Add to dashboard Cite

Ion implantation, with its good control of dose, is an attractive technique for producing doped layers in silicon devices and has been used for many different applications. However, the implantation process involves disruption of the lattice and defects are formed, which can degrade device properties. Methods of minimizing the damage will be discussed and direct comparisons made between implantation and diffusion techniques in terms of defects in the final devices and the electrical performance of the devices.Defects are produced in the silicon lattice during implantation but they are annealed to form secondary defects even at room temperature. We are not therefore concerned with primary defects but those produced after annealing. The annealing can be at a low temperature ( ~9 0 0 "C) when migration of defects in silicon is generally small, or at a high temperature when they can grow well beyond the implanted region. The defect structures can be complicated by impurity atoms knocked into the silicon from surface layers by the implantation. Defects can also be produced within layers on top of the silicon and these can be very important in device fabrication. In addition to affecting the electrical properties of the final device, defects produced during fabrication may influence the chemical properties of the materials. The use of these properties to improve devices will be discussed as well as the degradation they can cause.

show abstract

Section: 2 Reduction In Carrier Lifetimesupporting

confidence: 66%

Implantation damage in silicon devices

Nicholas¹

1977

J. Phys. D: Appl. Phys.

View full text Add to dashboard Cite

show abstract

“…Although the relationship between device operating stress and defect density is unknown, the evidence of strong correlation between leakage current and defect density have been found through implantation process [1]. One possible defect which might cause the ICBO and li FE degradations is the interface damage.…”

Section: Discussion On Gain-degradation Mechanismsmentioning

confidence: 98%

“…Considering the operating point of a transistor, which is determined by the bias voltages, V BB and V C c< and resistors, we have chosen the conditions of fixed V BB and Vcc instead of a fixed I c in the measurements of I/FE, y BE, and V CE for the study of device degradation. Since V BE =I B r BB >+V BE > (1) where V BE ' is the barrier potential across B-E junction and r BB > is the base resistance, the variation of V BE may reveal changes inside the DUT such as the temperature change of B-E junction or resistance changes in current paths of /«. Similarly, VCE is affected by collector resistivity.…”

Section: Analysis Of Gain-degradation Datamentioning

confidence: 99%

Current‐gain degradation and failure‐rate prediction in bipolar junction transistors

Liu

Lee

1987

Journal of the Chinese Institute of Engineers

View full text Add to dashboard Cite

Although dc current gain has been widely treated, its relation to device reliability is still unavailable. We show here that the variation of current gain of bipolar junction transistors depends upon device operating time and may be used as a failure indicator in case no failure occurs in a test. From the accelerated test data with zero failure, a method for the computation of device age is illustrated and compared with traditional methods. Owing to the composite nature of current gain, we obtain an empirical formula which is useful in providing us a quantitative anticipation of device life. A current gain degradation mechanism is also discussed.

show abstract

“…The point defects, interstitials, and vacancies recombine, eliminating damage. Both pointdefect species can cluster, and frequently interstitial-rich extended defects are observed [17][18][19][20]. As the defects recombine and cluster, they can also interact with dopants.…”

Section: Figurementioning

confidence: 99%

Process modeling for future technologies

Law

2002

IBM J. Res. & Dev.

View full text Add to dashboard Cite

Process modeling is an integral portion of technology computer-aided design (TCAD) and can be used to predict device structures and doping. Truly predictive process modeling has proven to be an elusive goal, because the controlling physics is complicated and difficult to investigate experimentally. The current state of process modeling is reviewed, and current and future challenges are discussed. Recent helpful trends are indicated, and problems that must be addressed are identified.

show abstract

Effects of dislocations in silicon transistors with implanted bases

Cited by 39 publications

References 13 publications

Implantation damage in silicon devices

Implantation damage in silicon devices

Current‐gain degradation and failure‐rate prediction in bipolar junction transistors

Process modeling for future technologies

Contact Info

Product

Resources

About