Effects of Gate Oxide and Junction Nonuniformity on the DC and Low-Frequency Noise Performance of Four-Gate Transistors

Jiménez-Tejada, J.A.; Rodriguez, A. Luque; Godoy, A.; Rodríguez‐Bolívar, S.; López‐Villanueva, J. A.; Marinov, O.; Deen, M. Jamal

doi:10.1109/ted.2011.2176494

Cited by 19 publications

(3 citation statements)

References 39 publications

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“…In other words, the mobility decreases because of weak inversion of oxide and interface charges [58]. Hence, for high temperature exposed, the effect is mostly influenced by oxide and interfaces traps on Si–SiO 2 interface [59] which eventually brings down the mobility. Furthermore, due to the decreasing mobility of electrons, the delay of the inverters decreased.…”

Section: Results and Analysismentioning

confidence: 99%

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Jaafar

Soin²,

Hatta³

et al. 2019

IET Computers & Digital Techniques

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Thermal issues are rapidly evolving in the field-programmable gate arrays (FPGAs) and are being intensely studied as these issues appear to significantly affect the delay performance of FGPAs. A ring oscillator has been widely used as a digital temperature sensor to sense this thermal effect on FPGAs. The delay generated by the ring oscillator will vary depending on the temperature environment due to negative bias temperature instability, hot carrier injection and electromigration. It is therefore critical to adopt an accurate ring oscillator design to effectively measure the delay in FGPAs. In this study, a digital temperature sensor with a stable ring oscillator is proposed. Measurement periods of 512 and 4096 clock cycles have been implemented and the relationship between temperature, delay and total count has been established. The results show that as the temperature increases to 100°C, the delay decreases by 3.99 and 33.98% for 512 and 4096 clock cycles, respectively. It has been found that in order to reduce the degradation effect on the Virtex-6 FPGA, adopting a measurement period of 512 clock cycles is the best method. The measured data is successfully validated through a set of simulations. Thus, it may benefit a system designer and industrial player, especially in designing temperature-based FPGAs.

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Section: Results and Analysismentioning

confidence: 99%

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Jaafar

Soin²,

Hatta³

et al. 2019

IET Computers & Digital Techniques

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show abstract

“…( 11) may meet with difficulties in the practice of characterization of advanced structures. For instance, in later publications [265,266] there were found operating regions in this transistor where the cutoff frequency of the Lorentzian spectra, originated by volume deep centers, changed with gate voltage. This result contradicts the classical assumption that no variation of the cutoff frequency occurs in Lorentzians related to a given trap level in the depletion layer of an MOS transistor.…”

Section: Vi15 Two-mos Two-junction Gate Transistormentioning

confidence: 90%

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

2022

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“…Depending on the film thickness of SOI transistor and bias voltages applied to the four independent gates, G 4 FET can work in several different operating regimes. Thorough investigation on different possible operating regions have been done based on analytical work, numerical simulation, and experimental results [14–20]. Still, for simulating circuits containing G 4 FETs, a suitable SPICE model is needed which will work with reasonable accuracy and efficiency in different operating conditions.…”

Section: Introductionmentioning

confidence: 99%

DC modelling of SOI four‐gate transistor (G ⁴ FET) for implementation in circuit simulator using multivariate regression polynomial

Hasan

Islam

2018

IET Circuits, Devices & Systems

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An efficient numerical model of silicon-on-insulator (SOI) four-gate transistors (G 4 FET) and its implementation in circuit simulator is presented here. A set of available data for different operating conditions is used to empirically determine the parameters of this model and a different set of test data is used to verify its predictive accuracy. This DC model is used to express the drain current as a single multivariate regression polynomial with its validity spanning across different possible operating regions as long as the chosen independent variables lie within the range of data set used to develop the model. The continuity of the polynomial model and its derivatives makes it particularly suitable for implementation in a circuit simulator. Models for both n-channel and p-channel G 4 FETs have been developed and validated using TCAD and experimental data and are successfully implemented in SPICE simulator for simulating two experimentally demonstrated G 4 FET circuits.

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Effects of Gate Oxide and Junction Nonuniformity on the DC and Low-Frequency Noise Performance of Four-Gate Transistors

Cited by 19 publications

References 39 publications

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

DC modelling of SOI four‐gate transistor (G ⁴ FET) for implementation in circuit simulator using multivariate regression polynomial

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Effects of Gate Oxide and Junction Nonuniformity on the DC and Low-Frequency Noise Performance of Four-Gate Transistors

Cited by 19 publications

References 39 publications

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

DC modelling of SOI four‐gate transistor (G 4 FET) for implementation in circuit simulator using multivariate regression polynomial

Contact Info

Product

Resources

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DC modelling of SOI four‐gate transistor (G ⁴ FET) for implementation in circuit simulator using multivariate regression polynomial