Effects of Hot Carrier Stress on Reliability of Strained-Si Mosfets

Dey, S.; Agostinelli, M.; Prasad, C.; Wang, X.; Shifren, L.

doi:10.1109/relphy.2006.251262

Cited by 5 publications

(6 citation statements)

References 6 publications

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“…Further voltage reduction, however, is unlikely for the near term as we continue to introduce newer technologies/processes. For example, the HCI impact of strained silicon is unclear [14][15]. Therefore, with no planned V dd reductions, and with the introduction of new processes/materials such as strained silicon, HCI effects will have to be reinvestigated relative to their impact on circuit degradation.…”

Section: Impact Of Scaling On Nbtimentioning

confidence: 99%

Reliability Trends with Advanced CMOS Scaling and The Implications for Design

McPherson

2007

2007 IEEE Custom Integrated Circuits Conference

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Scaling (for enhanced performance, increased functionality and cost reduction reasons) has pushed existing CMOS materials much closer to their intrinsic reliability limits. This will require that designers pay very close attention to both front-end-of-line (FEOL) and back-end-of-line (BEOL) reliability issues. As for the FEOL reliability issues, hyperthin gate oxide leakage, time-dependent dielectric breakdown (TDDB), and negative-bias temperature instability (NBTI) are near the top the list. In the case of hyper-thin gate oxides, TDDB can manifest itself in terms of multiple soft-breakdown events thus causing an unwanted rise in leakage; NBTI-induced p-channel device degradation tends to have a significant impact on minimum-voltage circuit operation. As for the important BEOL reliability issues, the top ones are: electromigration (EM), stress migration (SM), low-k dielectric TDDB, and mechanical weaknesses associated with the low-k films and their interfaces. The EM associated with Cu interconnects will continue to worsen with scaling due to increased interface effects; SM will require even fewer vacancies to coalesce which can cause an unwanted via resistance rise; and, relatively poor low-k TDDB behavior and low-k mechanical-weakness issues may require special interconnect layout considerations.

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Section: Impact Of Scaling On Nbtimentioning

confidence: 99%

Reliability Trends with Advanced CMOS Scaling and The Implications for Design

McPherson

2007

2007 IEEE Custom Integrated Circuits Conference

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“…Increase occurs because concentrated electric field at the gate end is reduced. 32 It is worth noting that maximum breakdown for thicker buffer is significantly higher with peak around L GD = 7um. It can be attributed to impact ionization and surface traps where it can be speculated that increase in L GD enhances the impact ionization rate that contributed to enhancement of breakdown voltage.…”

Section: Device Performance and Discussionmentioning

confidence: 95%

“…This detriments electron mobility by impacting density of states and effective mass and also by incrementing gate current and hot carrier effects. 32 Stress is also a major performance parameter in terms of reliability and can cause heavy device degradation if not examined properly. Stress may result from mismatch of lattice constant and thermal expansion coefficient and causes similar consequences like strain.…”

Section: Device Performance and Discussionmentioning

confidence: 99%

“…This is beneficial because it helps to reduce the large vertical field under the gate and hence improve carrier trapping phenomena by reducing trapping centers. 32 Both stress and strain are induced extensively due to inverse piezoelectric effect and heavily influenced by the electric field distribution. There is also strong correlation between the type of strain/stress in AlGaN/ GaN and the V th shift.…”

Section: Device Performance and Discussionmentioning

confidence: 99%

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Analytical Optimization of AlGaN/GaN/AlGaN DH-HEMT Device Performance Based on Buffer Characteristics

Rahman

Hatta

Soin

2019

ECS J. Solid State Sci. Technol.

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In this paper, conventional DH-HEMT has been optimized extensively to achieve improved breakdown characteristics while retaining efficient confinement of 2DEG in the buffer and channel. Critical Figures of Merit (FOMs) including DC and stress was analyzed in addition using Synopsys’ Sentaurus TCAD tool, to address recent challenges with single heterojunction HFET. Four different epitaxial designs were tactically manipulated by considering different materials for substrate and buffer. Investigation was executed from multiple aspects. Significant observation includes enhancement of breakdown voltage to 580V with extremely low gate leakage current and adequate carrier mobility in the channel. This is due to suppression of parasitic conduction path usually observed in conventional device. However, low DC output was recorded. The proposed structure was further optimized through important geometric consideration rendering its application in power switching, next generation communication system and radar application. Extensive TCAD modelling was implemented to precisely ensure complexity of heterostructure devices.

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“…16,23,[35][36][37] Due to its technological importance, the impact of external mechanical stress on HCI has been aggressively studied, showing opposite trends. 23,[35][36][37][38] Two strain-related models can explain this discrepancy: ͑1͒ a decrease in charge trapping in relatively thick gate dielectric via strain-altered trap activation energy 23,35,36 and ͑2͒ straininduced Si band gap narrowing and an increase in impact ionization at the drain edge. 37,38 For both uniaxial tensile and compressive stresses, a decrease in a trapping of injected hot carriers in high-k likely results in an improved HCI, 25,31 while an increase in impact ionization may multiply the number of hot carriers, leading to a degradation of HCI.…”

Section: Hci and V Th Instabilitymentioning

confidence: 99%