Effects of independent double-gated configuration on polycrystalline-Si nonvolatile memory devices

Abstract

A polycrystalline-Si thin-film transistor configured with independent double-gated structure and ultrathin channel film is proposed for use as a Si-oxide-nitride-oxide-Si memory device. Taking advantage of additional control gate bias offered by the independent double-gated scheme in addition to the driving gate, this work demonstrated that the reading window and programming efficiency can be improved by applying a proper control gate bias. It is also found that the relationship between programming/erasing speed and control gate bias is strongly related to channel film thickness. Our results indicate that the independent double-gated device possesses promising potential for future nonvolatile memory applications.

Investigations of an Independent Double-Gated Polycrystalline Silicon Nanowire Thin Film Transistor for Nonvolatile Memory Operations

“…[15][16][17] In light of this and employing a very simple and low-cost procedure, we have recently proposed an IDG poly-Si NW TFT as a SONOS-type memory device. 18,19) We found in ref. 18 that the threshold voltage (V TH ) windows under two feasible read modes (i.e., read by two different gates) show distinctly different dependences on the auxiliary gate (AG) bias.…”

“…Here, the device is programmed by applying V G2 ¼ 16 V and varying V G1 , and is read by the SG-2 mode with V G1 ¼ 0 V. As reported in ref. 18, during programming, a positive AG bias can help induce an additional number of electrons that are available for tunneling into the nitride layer, while a negative one tends to deplete electrons present in the channel. In this regard, the V TH shift for a given programming time in Fig.…”

“…10 is completely opposite to that in ref. 18, where severe electron injection from the gate electrode during erasing due to the use of a thin blocking oxide layer results in a low erasing speed so that the effect of AG bias observed therein may not represent the entire picture. In contrast, the reasonable erasing efficiency in Fig.…”

Insight into the performance enhancement of double-gated polycrystalline silicon thin-film transistors with ultrathin channel

“…1 Such concern can be relieved by thinning the channel to reduce the amount of defects 4,5 and/or the adoption of a multiple-gated configuration to enhance the gate controllability. [5][6][7] The latter approach has also been widely investigated in devices with monocrystalline Si channel. 8,9 By combining the above two approaches, SS smaller than 100 mV/dec can be achieved.…”

Fabrication of High-Performance Poly-Si Thin-Film Transistors With Sub-Lithographic Channel Dimensions

“…It should be noted that, in order to capitalize the above capability, the planar width of the channel in the multiple-gated configurations need to be shrunk as well [7]. Previously, we've presented several approaches to define the poly-Si nanowire channels using conventional G-line or I-line based lithography [10]- [12]. However, the minimum channel length is around 400 nm as imposed by the limitation of I-line lithography.…”