Effects of nitridation of silicon and repeated spike heating on the electrical properties of SrTiO3 gate dielectrics

Abstract

Electrical properties of SrTiO3 (STO) gate dielectrics on Si substrates grown by rf-magnetron sputtering were studied. We employed the surface nitridation and repeated spike heating to improve the interfacial properties of STO/Si. The nitrogen was moderately incorporated at the interface by first growing a thin SiON layer and then removing this sacrificial layer before growing STO gate dielectric. The experimental results indicate that this nitridation treatment may retard the formation of thin interfacial layer during the high-temperature growth of STO gate dielectric and consequently decrease the equivalent oxide thickness (EOT) by about 10% toward 24% at various deposition pressures. The STO gate dielectric with this nitridation treatment exhibited slightly lower leakage current at an accumulation region and nearly 2 orders of magnitude lower leakage current at an inversion region. The repeated spike heating technique was also employed to deposit a STO gate dielectric at repeated oscillating temperatures. The results show that this thermal treatment reduced the interfacial trap states and the leakage current was also reduced by about 1 order of magnitude at the same EOT.

HIGH-k GATE DIELECTRIC: AMORPHOUS Ta/La2O3 FILMS GROWN ON Si AT LOW PRESSURE

“…However, the incorporation of a certain amount of nitrogen into the substrate surface may improve the interfacial properties due to the depression of the formation of the interfacial layer during the high-temperature growth of gate dielectrics. 5 The optical bandgap (E g Þ of Ta/La 2 O 3 sample is studied by UV-visible optical absorbance spectra according to the following function:…”

“…[1][2][3] Further, thinner SiO 2 gate dielectric poses complex integration issues related to the penetration of impurities such as boron through thin gate, nonuniform oxide growth and reliability. 4,5 Improvement in thin¯lm processing can solve most of these issues, except the high gate leakage current caused by direct tunneling, which is the fundamental physical limit in device scaling. 6 The straightforward solution is to replace the conventional SiO 2 with alternative materials with high dielectric constant (high-k).…”

SrTiO3–SiO2 oxide films for possible high-k gate dielectric applications

“…Among the various possible candidates of high-k gate dielectrics, SrTiO 3 (STO) plays a good role because of its large dielectric constant [6,7]. However, the crystallization temperature of STO is too low to conform to the integration technology.…”

Conduction Behavior of V-SrZrO3 Thin Film Showing Resistive Switching

“…NVM with a metal-insulator-metal (MIM) sandwich structure is potentially ideal due to the small cell size and few mask layers needed for fabrication. Resistive random access memory (RRAM), being one kind of NVMs, offers the potential of high density integration for the fact that the resistance is changed simply by applying a voltage pulse without the need of a large reset current for phase change [1]. The polarity and magnitude of voltage or pulse required for each on/off transition are different for various metal oxides.…”