Effects of Package Level Structure and Material Properties on Solder Joint Reliability Under Impact Loading

Fan, Xuejun; Ranouta, Amarinder Singh; Dhiman, Harpreet S.

doi:10.1109/tcpmt.2012.2217744

Cited by 13 publications

(4 citation statements)

References 18 publications

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“…Design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability [16]. Xuejun Fan et al pointed that, for a copper post (or pillar) WLP, wafer level epoxy, which encapsulated copper pillars, served as a compliant layer for solder joint stress reduction under dynamic loading [17]. In this paper, the drop reliability and the failure mode of this kind of WLCSP were discussed.…”

mentioning

confidence: 94%

Drop failure modes of a wafer-level chip-scale packaging

Huang

Liu

Zhao

et al. 2013

2013 14th International Conference on Electronic Packaging Technology

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The present work evaluated the board level reliability of a kind of wafer-level chip-scale packaging (WLCSP). Drop impact tests were conducted to evaluate the lifetime and failure mode of the components before and after thermal cycles from -55 to 125 o C (50, 100, 150 temperature cycles) and high temperature (125 o C) storage (50 h, 100 h, 150 h). Under the peak acceleration of 1500 g and pulse duration of 0.5 ms, no failures were found in all of the components experienced thermal treatments after 300 drops. For the components without thermal treatments, cracks generated after 5000 drops under the shock condition with the peak acceleration of 2900 g and the pulse duration of 0.3 ms. Three kinds of failure modes were observed. The first was resin crack that generated between Cu pad and PCB; the second was internal cracks in the solder joints which generated near the IMC layer on the component side; and the third one was fracture of the Cu pad near the component. Among the above three failure modes, resin cracks most likely occurred during drop tests. The solder joints in the first row that closed to the center of PCB were checked after drop tests. Resin cracks were generally emerged at the two corners of the components. The internal cracks of solder joints tended to occur in the third solder joints, due to the resin cracks in the first and second joints released the impact energy. The cracks in Redistribution Layer (RDL) and fracture of Cu pad near the component least happened and always coexisted with the other two kinds of cracks. From the perspective of locations of components, cracks more easily generated in the components near the edge of PCB.Keywords-Sn-3Ag-0.5Cu solder joint; board-level drop reliability; failure mode; wafer-level chip-scale packaging (WLCSP); intermetallic compound (IMC)

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mentioning

confidence: 94%

Drop failure modes of a wafer-level chip-scale packaging

Huang

Liu

Zhao

et al. 2013

2013 14th International Conference on Electronic Packaging Technology

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“…Drop tests of board level specimens are generally undertaken to evaluate the reliability of solder joints in IC packages subjected to shock or impact loading [12][13][14][15][16]. Interest in the mechanical properties of solder joints motivated direct ball impact tests on solder bumps bonded to substrates [17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

A Novel Method for Impact Testing of Small Specimens - Numerical Simulation and Experiments

et al. 2015

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A novel method for dynamic testing of small specimens, based on impact loading, is proposed. This is motivated by the desire to elicit the dynamic mechanical response of single solder joints measuring 0.5 mm smaller in size. Impact loading is generated through impact of a tubular striker against a loading plate which is initially in contact with the specimen. The mechanical response of the specimen is derived from noting the stress waves generated in slender bars attached to the loading plate and specimen. Through this approach, dynamic tension or compression can be conveniently applied using the same test apparatus, and exact alignment of the slender bars attached is not critical. In addition, wave dispersion or attenuation in the bars (e.g., when polymer bars are used) has much less influence on the accuracy of results obtained. The equations governing this novel approach are derived and validated by finite element modeling. A prototype of a miniature impact tester was consequently fabricated, and tests on small aluminum specimens showed results comparable to that employing traditional split Hopkinson bar systems. The test arrangement was utilized for dynamic testing of lead-free single solder joint specimens, and initial results obtained are presented.

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“…The market value of the fan-in WLCSP that was reported by Yole Development is more than $1.8 B in 2012 and is expected to increase to $2.7 B in 2016 [1]. Because high-performance WLCSP solutions are in high demand, the challenges of finer pitch, high I/O pin count, and solder joint reliability become important topics to be studied [2]- [11]. Moreover, a lowcost WLCSP solution is also an important requirement due to growing price pressures and inflationary cost of materials [12], [13].…”

Section: Introductionmentioning

confidence: 99%

Finite Element Analyses for Critical Designs of Low-Cost Wafer-Level Chip Scale Packages

Hsieh¹

2014

IEEE Trans. Compon., Packag. Manufact. Technol.

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With the advantages of high performance and low cost, the wafer-level chip scale package (WLCSP) is widely used in integrated circuit fabrication today with rapidly growing demand in the semiconductor packaging industry. As WLCSP moves toward thinner, smaller, lower cost, and fine-pitch package designs to meet the increasing requirements of electronic products, a lot of challenges need to be overcome. The most important challenge is preventing failure and enhancing package reliability. To understand the mechanical behaviors of WLCSP, comprehensive finite-element analyses (FEAs) for various WLCSP structures, including the general design with one under-bumpmetallurgy layer, one redistribution layer (RDL), and two polymer layers on a passivated wafer (called 2P2M WLCSP in this paper, which means that there are two polymer layers and two metal layers on the passivated wafer), the low-cost designs of 2P1M WLCSP (with two polymer layers and only one RDL on a passivated wafer) as well as 1P1M WLCSP (with only one polymer layer and one RDL on a passivated wafer) were carried out. Different parameters in WLCSP were investigated to look for critical factors that impact the corresponding stresses. Moreover, the board level reliability thermal cycling test that followed JEDEC standard was used, which suggested that the solder cracks were observed mostly near the intermetallic compound layer in WLCSP structures and aligned with the FEA results. Hence, by employing reliable modeling, not only can the critical factors that affect the stress responses be obtained but also can the proper parameters to provide the best reliability in WLCSP be determined. This paper offers a good reference and can effectively serve as design guidelines in cases of significant factor selection analyses on WLCSP designs.Index Terms-Finite-element analysis (FEA), parametric study, stress analysis, thermal cycling test (TCT), wafer-level chip scale package (WLCSP).

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Effects of Package Level Structure and Material Properties on Solder Joint Reliability Under Impact Loading

Cited by 13 publications

References 18 publications

Drop failure modes of a wafer-level chip-scale packaging

Drop failure modes of a wafer-level chip-scale packaging

A Novel Method for Impact Testing of Small Specimens - Numerical Simulation and Experiments

Finite Element Analyses for Critical Designs of Low-Cost Wafer-Level Chip Scale Packages

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