Effects of pulsed current on electromigration lifetime

Diffusivity variation in Electromigration failure

“…16,17] have published line resistance plots under periodic bidirectional stress. References [16] and [17] are interesting in particular due to the contrasting test structures used.…”

“…16,17] have published line resistance plots under periodic bidirectional stress. References [16] and [17] are interesting in particular due to the contrasting test structures used. In [16] a Cu/SiCOH interconnect test structure is used, from a 65 nm CMOS process; single damascene at the lowest metal layer M1 and dual damascene at metal layers M2 and M3.…”

“…References [16] and [17] are interesting in particular due to the contrasting test structures used. In [16] a Cu/SiCOH interconnect test structure is used, from a 65 nm CMOS process; single damascene at the lowest metal layer M1 and dual damascene at metal layers M2 and M3. The Cu M2 test line (200μm  0.3μm) is connected to broader lines (several μm wide) in M1 at one end and in M3 at the other.…”

“…[17] but might be different in ref. [16]. Once a void covers the electron path (v(t) = v cr ) the shunting through the liner causes a step increase in the line resistance R(t) denoted by R step [17]; R(t) then increases at a constant rate  (per void volume).…”

“…From the structure shown in Fig. 6 [16] it might be expected that, under downstream electron current stress (i.e. M3M2 M1), a small slit-like void will nucleates at V2 (via above) at a smaller critical volume than that of the larger void (via below) which will nucleates at V1 under similar upstream electron current conditions (i.e.…”