Effects of Si-cap thickness and temperature on device performance of Si/Ge_1−xC_x/Si p-MOSFETs

Abstract

This work presents the effects of Si-cap thickness and temperature on device performance of buried channel Si/Ge 1−x C x /Si p-MOSFETs. The silicon-cap thickness (3-9 nm), as well as the operating temperature (300 K down to 77 K), plays a significant role on device performance in terms of drive current, sub-threshold slope, effective hole mobility and I on -I off ratio. The 7 nm Si-capped device demonstrates highest mobility enhancement because of reduced remote Coulomb scattering. In addition, the valence band offset between the Si-cap/Ge 1−x C x interface was quantitatively extracted by fitting the stair-case behavior of split C-V characteristics with self-consistent simulations of one-dimensional Poisson and Schrodinger equations.

Role of Confinement on Carrier Transport in Ge–SixGe1–x Core–Shell Nanowires

“…This finding is consistent with the larger valence band offset of the Ge/Si 0.7 Ge 0.3 by comparison to the Ge/Si 0.5 Ge 0.5 core−shell interface, which requires higher (i.e., more negative) gate biases to induce holes in the shell (Figure 4a: dashed ellipses). We note that this finding is also in agreement with similar studies in planar Si/Ge heterostructures, 32 where the peak mobility is reached at a gate bias required to populate the second subband localized primarily in the Si cap layer. Figure 4b shows μ eff versus T for both heterostructures.…”