Effects of the stepped sidewall morphology on the ON-state performance for vertical GaN trench-gate MOSFETs

Tang, Wenxin; Zhou, Junzhi; Yu, Guo; Wei, Xing; Tang, Wenbo; Zhang, Li; Liu, Weining; Chen, Tiwei; Yu, Zicheng; Wang, Heng; Zhang, Xiaodong; Lin, Wenfang; Huang, Zhiwen; Huang, Rong; Cai, Yuanqiang; Zhang, Baoshun

doi:10.35848/1882-0786/ac727d

Cited by 5 publications

(3 citation statements)

References 26 publications

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“…Moreover, as shown also by 100 ns long pulsed characteristics, in some devices, a certain drain voltage was needed to initiate channel opening. Elsewhere, similar dc phenomenon was linked to rough morphology of p-channel side walls, [18] which in some cases might be analogous to our still un-optimized devices. Nevertheless, in our case, observed transients shorter than 200 ns are rather unique and needs further investigation.…”

Section: Resultssupporting

confidence: 64%

“…Values around 40 cm 2 V −1 s −1 reflect C‐doping in SI GaN, nevertheless, even without special surface pretreatment; our mobility data clearly outperform those by inversion in the typical p ‐GaN channel vertical transistor. [ 18 ] In the particular study, mobility value has increased from 4.5 to 14.6 cm 2 V −1 s −1 if 25% tetramethylammonium hydroxide solution treatment was applied after dry etching. High channel mobility is crucial for achieving a low loss switching.…”

Section: Resultsmentioning

confidence: 95%

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Vertical GaN Transistor with Semi‐Insulating Channel

Šichman

Stoklas

Hasenöhrl

et al. 2023

Physica Status Solidi (a)

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Herein, vertical GaN transistors with a semi‐insulating (SI) 1.3 μm thick channel layer and C doping of 1 × 1017 cm−3 are studied. Structures are grown using a metal–organic chemical vapor deposition on conductive GaN substrates. SI GaN is sandwiched between 2.5 μm thick n‐GaN drift layer (Si doping of ≈ 1 × 1017 cm−3) and a top n‐GaN contact layer. A circular mesa region with a diameter of 180 μm is patterned using a deep dry etching. The gate contact formed on the mesa sidewall is insulated from the vertical channel using a 20 nm thick Al2O3 grown by an atomic layer deposition. Despite a robust layout, transistors transfer characteristics indicate normally off behavior if extracted from the linearly scaled current–voltage characteristics and an open channel drain current of 30 mA at the gate bias of 4 V. Achieved on/off ratio is 107 at −2 V subthreshold gate bias when the full channel depletion is reached. And, 200 ns long gate pulse characteristics show only a marginal trapping even though no post‐metallization annealing is performed. By comparing experimental results with modeling, mobility of free electrons in the channel is found to be about 45 cm2 V−1 s−1.

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Section: Resultssupporting

confidence: 64%

Section: Resultsmentioning

confidence: 95%

Vertical GaN Transistor with Semi‐Insulating Channel

Šichman

Stoklas

Hasenöhrl

et al. 2023

Physica Status Solidi (a)

View full text Add to dashboard Cite

show abstract

“…On one hand, it decides whether step-flow growth can proceed steadily together with atomic diffusion length [5−7] ; on the other hand, many researchers have found it closely related to the incorporation of indium [8] or aluminum atoms [9−14] and impurities such as carbon [15] , magnesium [16] and oxygen [17] . Moreover, etch-then-regrow method has shown great prospects for LDs grown on stripes of silicon substrates [18] , normally-off HEMTs [19] . The device performance is hugely affected by the smoothness of the shape of sidewalls on vertical trench-gate MOSFETs [20] .…”

Section: Introductionmentioning

confidence: 99%

Controllable step-flow growth of GaN on patterned freestanding substrate

Wu,

Liu,

et al. 2024

J. Semicond.

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A new kind of step-flow growth mode is proposed, which adopts sidewall as step source on patterned GaN substrate. The terrace width of steps originated from the sidewall was found to change with the growth temperature and ammonia flux. The growth mechanism is explained and simulated based on step motion model. This work helps better understand the behaviors of step advancement and puts forward a method of precisely modulating atomic steps.

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Enhancement-mode β-Ga2O3 U-shaped gate trench vertical MOSFET realized by oxygen annealing

Zhou

et al. 2022

Applied Physics Letters

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Vertical metal–oxide–semiconductor field effect transistor (MOSFET) is essential to the future application of ultrawide bandgap β-Ga2O3. In this work, we demonstrated an enhancement-mode β-Ga2O3 U-shaped gate trench vertical metal–oxide–semiconductor field effect transistor (UMOSFET) featuring a current blocking layer (CBL). The CBL was realized by high-temperature annealing under oxygen ambient, which provided electrical isolation between the source and drain electrodes. The CBL thicknesses of different annealing temperatures were derived from C–V measurements and the Fermi level position of the sample surfaces of different annealing temperature was characterized by x-ray photoelectron spectroscopy measurements, indicating good process controllability. Furthermore, photoluminescence spectra were measured to study the effect of oxygen annealing. The fabricated UMOSFET showed normally off with a Vth of 11.5 V, an on-state resistance of 1.48 Ω cm2, a maximum on-state current of 11 A/cm2, an on–off ratio of 6 × 104, and a three-terminal breakdown voltage over 100 V. This work paves a way to form a CBL and broadens the design space for high-power β-Ga2O3 vertical transistors.

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Effects of the stepped sidewall morphology on the ON-state performance for vertical GaN trench-gate MOSFETs

Cited by 5 publications

References 26 publications

Vertical GaN Transistor with Semi‐Insulating Channel

Vertical GaN Transistor with Semi‐Insulating Channel

Controllable step-flow growth of GaN on patterned freestanding substrate

Enhancement-mode β-Ga2O3 U-shaped gate trench vertical MOSFET realized by oxygen annealing

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