Effects of Thermal Treatments on the Trapping Properties of HfO$_{2}$ Films for Charge Trap Memories

Abstract

The charge trapping properties of HfO2 thin films for application in charge trap memories are investigated as a function of high-temperature postdeposition annealing (PDA) and oxide thickness in the TaN/Al2O3/HfO2/SiO2/Si structure. The trap density (NT) in HfO2, extracted by simulating the programming transient, is in the 1019–1020 cm-3 range, and it is related to film thickness and PDA temperature. Diffusion phenomena in the stack play a significant role in modifying NT in HfO2 and the insulating properties of the Al2O3 layer. The memory performances for 1030 °C PDA are promising with respect to standard stacks featuring Si3N4.

The interface inter-diffusion induced enhancement of the charge-trapping capability in HfO2/Al2O3 multilayered memory devices

“…Also, a first-principles study reported by Hou et al 26 showed that both the substitution of Al for O and the interstitial Al could introduce deep trap levels in the band gap of HfO 2 . So the inter-diffusion at the interface HfO 2 /Al 2 O 3 can create a lot of trap sites in the charge trapping layer, which is consistent with the viewpoints of Spiga et al 27 As the number of Al 2 O 3 intercalation layers increases, the total thickness of the inter-diffusion layers takes a larger proportion in the total thickness of the charge trapping layer. So more trap sites can be created in the charge trapping layer, resulting in the improvement of the charge trapping merit.…”

The roles of the dielectric constant and the relative level of conduction band of high-k composite with Si in improving the memory performance of charge-trapping memory devices

“…5,15 A deep-trap-site model was proposed and also supported by some experimental data, which suggests that the charges in CTM devices are trapped in the trap levels in the band gap, [16][17][18] and that the defect sites can be introduced by doping metal ions of different coordination number with native metal ions in the charge-trapping dielectric, or by fabricating an interface of different high-k dielectrics. 19,20 The density and size of ZrO 2 NCs were reported as the critical factors affecting ZrO 2 NCs CTM devices, indicating that the dielectric interface played an important role in the charge storage ability of CTM devices. 21 It was also reported that the multilayered high-k charge-trapping layer, such as HfO 2 /Al 2 O 3 /HfO 2 and ZrO 2 /Al 2 O 3 /ZrO 2 etc., causes an enhancement of the charge-storage efficiency of the CTM devices.…”

“…21 It was also reported that the multilayered high-k charge-trapping layer, such as HfO 2 /Al 2 O 3 /HfO 2 and ZrO 2 /Al 2 O 3 /ZrO 2 etc., causes an enhancement of the charge-storage efficiency of the CTM devices. [22][23][24][25][26] In our previous study, a remarkable charge-trapping efficiency and a fast programming/erasing(P/E) speed were obtained in a CTM device with a TiAlO high-k composite chargetrapping dielectric, achieving a density of trapped charges of 9.3×10 20 …”

“…20,27 Although many efforts have been made to improve the performance of the CTM devices with different high-k charge-trapping dielectrics, and some of which show excellent charge-storage efficiency, fast P/E speed, good endurance and retention characteristics, the comparative studies on the parameters of high-k dielectric affecting the electric performance of CTM devices have rarely been done. In this paper, we report the CTM devices containing a high-k composite charge-trapping layer (TiO 2 ) x (Al 2 O 3 ) 1-x (TiAlO)(nominal composition x = 0.05, 0.5 and 0.7), in which the dielectric constant of the composite and the band alignment with Si were adjusted by controlling the partial composition of TiO 2 .…”

Ta2O5-TiO2 Composite Charge-trapping Dielectric for the Application of the Nonvolatile Memory

“…With continuous down-scaling the cell dimension to obtain high data-storage density, high program/erase speeds, low operating voltage and low power consumption, some intrinsic limitations make this kind of memory rapidly approach the scaling limit, although 3D-architecture partly retards these challenges 5 . Various high-k dielectrics, such as HfO 2 , TiO 2 , ZrO 2 , Y 2 O 3 and La 2 O 3 6–9 , etc., as well as multilayer charge-trapping layer HfO 2 /Al 2 O 3 /HfO 2 and ZrO 2 /Al 2 O 3 /ZrO 2 , have been employed to replace Si 3 N 4 in SONOS devices to achieve a longer endurance and better retention property 10–16 . As a high-k dielectric, Al 2 O 3 was also chosen as the tunneling and blocking layers in many similar memory devices due to its good chemical and thermal stability and large band offsets with Si 17, 18 .…”