Effects of thickness and geometric variations in the oxide gate stack on the nonvolatile memory behaviors of charge-trap memory thin-film transistors

P‐15: Student Poster: Charge Trap‐Based Synaptic Transistor Employing In‐Ga‐Zn‐O as Channel and Trap Layers for Bio‐Inspired Neuromorphic Computing

“…On the other hand, hysteresis window size decreased from 2.5 V to 1 V as the annealing temperature increased from 200℃ to 350℃. Hysteresis window is affected by the thickness of the tunneling layer and the trap density of the CTL [18,19]. However, the thickness of the tunneling layer barely changes with annealing temperature.…”

Superior Atomic Layer Deposition Technology for Amorphous Oxide Semiconductor Thin-Film Transistor Memory Devices

“…With respect to the ZnO charge-trapping layer, the ALD technique has been extensively adopted to deposit it for oxide semiconductor TFT memories. − Since ZnO films can be deposited at the low temperature of 100 °C with Zn­(C 2 H 5 ) 2 and H 2 O precursors, the ALD ZnO charge-trapping layer has been investigated for flexible a-IGZO TFT memory. For example, Kim et al fabricated an a-IGZO TFT memory with the ALD ZnO charge-trap layer on a poly­(ethylene naphthalate) (PEN) substrate, demonstrating a wide memory margin (25.6 V), fast programming (∼500 ns), and a retention time longer than 3 h at both room temperature and 80 °C .…”

“…So far, only ALD ZnO films have been used as the active channel of TFT memory. ,,, For instance, Kim et al reported an ALD ZnO TFT memory, in which a 44.8 nm ZnO channel layer was deposited from Zn­(C 2 H 5 ) 2 and H 2 O at 125 °C . In order to modulate the carrier concentration of the as-deposited ZnO channel, the device was annealed at 500 °C in O 2 for 1 h, hence exhibiting a saturation field-effect mobility of 6 cm 2 /V·s, an on/off current ratio of ∼10 5 , and a SS of 0.7 V/decade.…”

Synergic Impacts of CF4 Plasma Treatment and Post-thermal Annealing on the Nonvolatile Memory Performance of Charge-Trap-Assisted Memory Thin-Film Transistors Using Al–HfO2 Charge Trap and In–Ga–Zn–O Active Channel Layers

“…Amorphous oxide semiconductors (AOSs) have been attracting much attention as active layers to replace polycrystalline silicon channels for advanced three-dimensional device structures due to various advantages such as high mobility, low-temperature compatibility, and grain-boundary-free uniform natures. − Alternatively, charge-trap-assisted memory thin-film transistors (CTM-TFTs) utilizing AOS channels, in which the charges are stored in localized trap sites within the charge-trap layers (CTLs), can be promising candidates as next-generation nonvolatile memories (NVMs), which are featured to have such advantages as a low operating voltage, excellent operational reliabilities, and compatibility with complementary metal oxide semiconductor technology (CMOS). − With the aim of realizing highly functional nonvolatile CTM-TFTs, various strategies, such as the introduction of high-dielectric-constant (high-k) CTLs, − CTL engineering, − and interfacial treatments between the tunneling layer (TL) and CTL, − have been investigated in order to enhance the program/erase (P/E) efficiencies and NVM reliabilities with improving the CTL trap densities and interfacial qualities. Alternatively, the continuous device scaling urges to further reduce the physical thickness of the gate stacks including the CTL and TL, and hence, the conventional CTM devices employing silicon nitride (Si 3 N 4 ) CTLs have faced the critical limit of a trade-off relationship between P/E speed and memory retention time. , Therefore, to overcome this problem and enhance the memory characteristics in terms of charge-trapping efficiency and equivalent oxide thickness (EOT) scaling, we previously demonstrated the NVM characteristics assisted by charge-trap/detrap events of the CTM-TFTs using oxide semiconductor materials, such as ZnO, − ,− In–Ga–Zn–O, (IGZO), and Hf-doped ZnO, as CTLs. Irrespective of successful demonstrations on previously reported CTM-TFTs employing the oxide channel, the choice of oxide semiconductor CTLs needed to be patterned with a double-layered tunneling oxide to avoid chemical damages induced into the channel layer during the patterning process .…”