Efficiency and Linearity of Digital "Class-C Like" Transmitters

A 39 W Fully Digital Wideband Inverted Doherty Transmitter

“…For the DTX hardware used, the minimum achievable duty-cycle is 40 % at the targeted RF operating frequency of 2.0 GHz by using on-chip duty-cycle adjustment. This sets the maximum theoretical achievable efficiency for these conditions to 75.7 %, while providing 21 % higher output power compared to analog class-B, assuming an ideal device and lossless output matching network [3]. Similar to the analog transconductance classes, digital class-C operation demands close to short-circuited conditions for its higher harmonics.…”

“…Digital class-C operation [3,4] was selected as operating class in this work for the DTX output stages; its capability to handle a relatively large output capacitance, its linear operation, limited voltage swing and excellent efficiency-output power relation motivated this choice [3]. Lowering the duty-cycle in digital class-C operation increases the efficiency at the cost of RF output power.…”

“…In the work of [2] and [3], focus was placed on achieving high DTX RF output power and peak efficiency; however, neither works offer enhanced efficiency in PBO, nor high RF BW. With this work, we present world's first fully-digital high-power Doherty transmitter (P out > 39 W).…”

High-Power Digital Transmitters for Wireless Infrastructure Applications (A Feasibility Study)

“…The latter can be handled by adopting a dedicated (nonlinear) segmentation technique [11] or by using digital predistortion (DPD) [15], [16]. In theory, g m scaling can provide linear DTX operation [17], but this approach relies on a transconductance class of operation, yielding constraints in efficiency while being potentially more sensitive to variations of the driving voltage of the gate segments (see also Sections IX-B and IX-C).…”

“…Furthermore, in the class-E operation, the supply voltage needs to be lowered to 20 V to avoid breakdown, lowering the output power capability [20]. Due to requirements on the effective R ON and to allow for some design flexibility (e.g., use of Cartesian operation, requiring I and Q banks, or flexibility to use operating classes with lower output power capability, such as digital class-C [17], in later implementations), we assume doubling of the minimum bank size with respect to an analog Class-B implementation at V LD = 28 V for 20-W RF output power, giving a minimum LDMOS total gate width W G,tot ≥ 33.6 mm, which is split over the two banks [Fig. 6(a)].…”