Efficient algorithms for task mapping on heterogeneous CPU/GPU platforms for fast completion time

Li, Zexin; Zhang, Yuqun; Ding, Ao; Zhou, Husheng; Liu, Cong

doi:10.1016/j.sysarc.2020.101936

Cited by 15 publications

(2 citation statements)

References 22 publications

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“…ILP formulations were adapted for ARM big.LITTLE architecture to reduce communication costs among different cores [25] and CPU-GPU architecture to reduce the execution time of the critical path [26]. [32] modified the basic heuristic to consider the heterogeneous ratio, task graph structure, data partition, and data transfer time. [38] found a solution for less memory contention and energy consumption on heterogeneous MPSoCs by deleting solutions with small fitness values and updating the solution set.…”

Section: Related Workmentioning

confidence: 99%

Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based Parallelization

Wu,

Kumano,

Marume

et al. 2024

IEEE Access

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In this paper, we propose a model-based workflow to generate parallel code on a multiple instruction stream, multiple data stream (MIMD) processor with vector accelerator (MIMDV) from a Simulink model. Solving data-and task-parallelism is crucial during this process. For data parallelism, a RISC-V Simulink library written in vector codes was prepared for blocks with sufficient vector or matrix calculations. Moreover, large inputs can be divided, which means that tasks can be executed simultaneously using multiple cores. For task parallelism, integer linear programming (ILP) was designed to deploy tasks on scalar processing elements (SPEs) and a vector processing element (VPE) of MIMDV. The use of a vector library for a task and the number of SPEs a task uses were determined. To reduce the overhead, synchronization is realized by barrier wait, and execution is divided into multiple time intervals called layer. We propose a novel one-step ILP that accurately minimizes the parallel time of such a situation. Furthermore, we propose a two-step ILP to achieve reasonable performance in practical time. One step is SPE mapping, and the other is layer scheduling. We tested our methods using random task graphs and real-world applications on DR1000C, a type of RISC-V MIMD processor with a vector accelerator.

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Section: Related Workmentioning

confidence: 99%

Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based Parallelization

Wu,

Kumano,

Marume

et al. 2024

IEEE Access

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show abstract

“…A wide survey on this topic of partitioning techniques and benchmarks regarding combined CPU/GPU architectures can be found in [52]. Among the many, it is worth mentioning the work of Li et al [44], which presents a set of algorithms for task mapping in heterogeneous platforms with GPUs, with the goal of minimizing the makespan.…”

Section: Related Workmentioning

confidence: 99%

Optimized Partitioning and Priority Assignment of Real-Time Applications on Heterogeneous Platforms with Hardware Acceleration

Casini,

Pazzaglia,

Biondi

et al. 2022

Preprint

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Hardware accelerators, such as those based on GPUs and FPGAs, offer an excellent opportunity to efficiently parallelize functionalities. Recently, modern embedded platforms started being equipped with such accelerators, resulting in a compelling choice for emerging, highly computational intensive workloads, like those required by next-generation autonomous driving systems. Alongside the need for computational efficiency, such workloads are commonly characterized by real-time requirements, which need to be satisfied to guarantee the safe and correct behavior of the system. To this end, this paper proposes a holistic framework to help designers partition real-time applications on heterogeneous platforms with hardware accelerators. The proposed model is inspired by a realistic setup of an advanced driving assistance system presented in the WATERS 2019 Challenge by Bosch, further generalized to encompass a broader range of heterogeneous architectures. The resulting analysis is linearized and used to encode an optimization problem that jointly (i) guarantees timing constraints, (ii) finds a suitable task-to-core mapping, (iii) assigns a priority to each task, and (iv) selects which computations to accelerate, seeking for the most convenient trade-off between the smaller worst-case execution time provided by accelerators and synchronization and queuing delays.

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A Survey on Heterogeneous CPU–GPU Architectures and Simulators

Alaei,

Yazdanpanah

2024

Concurrency and Computation

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Heterogeneous architectures are vastly used in various high performance computing systems from IoT‐based embedded architectures to edge and cloud systems. Although heterogeneous architectures with cooperation of CPUs and GPUs and unified address space are increasingly used, there are still a lot of open questions and challenges regarding the design of these architectures. For evaluation, validation and exploration of next generation of heterogeneous CPU–GPU architectures, it is essential to use unified heterogeneous simulators for analyzing the execution of CPU–GPU workloads. This article presents a systematic review on challenges of heterogeneous CPU–GPU architectures with covering a diverse set of literatures on each challenge. The main considered challenges are shared resource management, network interconnections, task scheduling, energy consumption, and programming model. In addition, in this article, the state‐of‐the‐art of heterogeneous CPU–GPU simulation platforms is reviewed. The structure and characteristics of five cycle‐accurate heterogeneous CPU–GPU simulators are described and compared. We perform comprehensive discussions on the methodologies and challenges of designing high performance heterogeneous architectures. Moreover, for developing efficient heterogeneous CPU–GPU simulators, some recommendations are presented.

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Efficient algorithms for task mapping on heterogeneous CPU/GPU platforms for fast completion time

Cited by 15 publications

References 22 publications

Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based Parallelization

Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based Parallelization

Optimized Partitioning and Priority Assignment of Real-Time Applications on Heterogeneous Platforms with Hardware Acceleration

A Survey on Heterogeneous CPU–GPU Architectures and Simulators

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