Efficient and Accurate Schematic Transistor Model of FinFET Parasitic Elements

Lu, Ning; Hook, T.B.; Johnson, J. B.; Wermer, C; Putnam, C.; Wachnik, R.

doi:10.1109/led.2013.2274511

Cited by 26 publications

(15 citation statements)

References 6 publications

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“…In the limit of large , , and , LI resistance in the case of a large contact resistance [given by (8)] reduces to (9) …”

Section: An Idealized Resistance Model For Unmerged Finsmentioning

confidence: 99%

“…This could simplify the characterization and modeling of diffusion resistance of FinFET devices. On the other hand, the parasitic resistance of local interconnect of a FinFET is not inversely proportional to fin number [9] and it can lead to different average drain currents from one fin to the next fin within a single FinFET device [10].…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we study the parasitic resistance in FinFET local interconnect in detail, covering both unmerged [9] and fully merged fin structures. We will present a set of resistance expressions that efficiently and accurately model the resistance in local interconnect (LI) for multiple cases of contact layout.…”

Section: Introductionmentioning

confidence: 99%

“…Due to the interconnections among horizontal resistive elements and vertical resistive elements , the horizontal resistive elements are not connected in series and vertical resistive elements are not connected in parallel, strictly speaking. Nevertheless, total S/D resistance (including local interconnect, diffusion, and contact resistances) can be calculated using a master resistance equation [9], (1) where is the resistance of the th S/D resistive element, is the electric current passing through the th S/D resistive element, and is the total drain current. Master (1) is the result of Thomson's principle: The total dissipated power is the sum of the power dissipated by individual resistive elements.…”

Section: Introductionmentioning

confidence: 99%

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Modeling of Resistance in FinFET Local Interconnect

Wachnik

2015

IEEE Trans. Circuits Syst. I

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We present an innovative and comprehensive approach to model the resistance of local interconnect used in FinFET technologies. Our parasitic resistance formulas for FinFET source/drain regions cover both merged and unmerged fin processes. Both simple and composite local interconnect cases are studied. They have been verified with field solver simulation results, and are found to be accurate over a wide range of parameter values. Our local interconnect resistance model has been used in IBM 14 nm SOI FinFET CMOS technology, and is a critical part of compact models used in both extraction flow and schematic/pre-layout flow.

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“…In the limit of large , , and , LI resistance in the case of a large contact resistance [given by (8)] reduces to (9) …”

Section: An Idealized Resistance Model For Unmerged Finsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Modeling of Resistance in FinFET Local Interconnect

Wachnik

2015

IEEE Trans. Circuits Syst. I

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“…The current through the multi-fin device depends on the location of the via contact and the bias condition. An efficient model (4) can predict the current accurately with a much simpler simulation as illustrated by the graphs on the right side of Figure 4. The effect is pronounced for the linear region with high gate drive and low darin bias.…”

Section: Source Drain Resistancementioning

confidence: 99%

(Invited) Parastic Elements in Gate Stacks and Contacts of Planar and Fin Transistors

Wachnik¹,

Lu²,

Lee³

et al. 2014

ECS Trans.

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Reduction of dimensions or scaling has reduced cost and enhanced performance of integrated circuits. These reduced dimensions have increased the importance of parasitic elements associated with the gate structure and contact structure to rf circuit design and more recently to microprocessors, standard products, and application specific integrated circuits. The net lists and compact models must account for the physical structure to enable scalability, must be efficient to enable circuit design and must be verifiable through hardware measurement. The hardware measurements can serve as a diagnostic tool for enhancing process technology of planar and FINFET field effect transistors. IntroductionControlling capacitance and series resistance of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been highlighted as a difficult process integration challenge in the 2012 ITRS overview (1). These parasitic elements have also been addressed in (2) with a focus beyond the MOSFET electrostatic and carrier transport problems. Gate resistance is a known problem in the design of radio frequency MOSFETs and is beginning to influence the design of digital logic (3). The past decade has seen an evolution from silicided poly-silicon on oxy-nitride to metal gate on Hi-K dielectrics. The method of integration has also evolved from gate first patterning practiced for decades to replacement metal gate schemes. Device contacts are evolving from lithographically aligned contacts to self aligned contacts and the evolution from planar devices to multi-gate or fin devices is driving the evolution of contact integration schemes from printed isolated contacts to local interconnect schemes which merge fins to minimize parasitic elements. High performance rf devices have used unique integration schemes to maximize performance, but these are not as attractive to microprocessors and system on chip technologies because of the cost to density.A related problem is providing an accurate representation of useful design information to circuit designers and hiding the process details which might hinder time to market of complex integrated circuits. In addition to geometric design rules and schematic checking of layout, compact models must balance accuracy with simulation runtime to minimize the impact of simulation time on circuit design. Developing and calibrating accurate models depends in part on elegant extraction of parameters through measurement. The next two sections discuss 1) the evolution of gate stacks and 2) the evolution of source drain contacts to identify the resistive components which should be incorporated into compact device models. Parasitic capacitive elements have been discussed extensively in (1), (2). Compact models of active silicon field transistors and other active devices are standardized with continuing improvements and will not be discussed here. 10.1149/06001.0003ecst ©The Electrochemical Society ECS Transactions, 60 (1) 3-8 (2014) 3 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. ...

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Modulation Doped FETs

Ding,

Zhu,

Ferreyra

et al. 2024

Encyclopedia of RF and Microwave Engineering

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Conventional modulation‐doped field‐effect transistors (MODFETs) with unprecedented performance, for example, a power gain of 15 dB at 190–235 GHz and a noise level of 1.2 dB with 7.2‐dB gain in the 90‐GHz range, have been demonstrated. Passivation process is of fundamental importance in the stability, good performance, and extension of device operative lifetime. We discuss strategies used to passivate the surface of GaAs and related compounds and GaN in the context of FETs. Recent research on the enhancement‐mode PMODFET (E‐PMODFET) variety for applications in high‐speed and low‐power digital circuits and power amplifiers with single power supply is described. Reliability of MOSFET based on GaAs is reviewed to some extent. Scalability issues as well as progress in FinFET‐based on InGaAs channel are summarized. Also to be noted is that III–V compound semiconductors as an alternative to Si as the channel material to improve the performance of metal‐oxide–semiconductor field‐effect transistors (MOSFETs) on Si platforms are a very attractive option for the next‐generation high‐speed integrated circuits but face serious challenges because of the lack of a high‐quality and natural insulator. III‐Nitride‐based HFETs showed tremendous performance in both high‐power RF and power‐switching applications. AlGaN/GaN‐based high‐power HFETs on SiC substrate with 60‐nm gate lengths have achieved maximum oscillation frequency of 300 GHz. On‐resistance of 1.1–1.2 Ω mm as well as drain current of ∼0.9 A/mm was also achieved. For HFET devices operated in class AB mode on GaN semiinsulating substrates, a continuous‐wave power density of 9.4 W/mm was obtained with an associated gain of 11.6 dB and a power‐added efficiency of 40% at 10 GHz. III‐Nitride devices for power‐switching application have achieved near‐theoretical limit for vertical devices‐based GaN native substrates and breakdown voltage as high as 1200 V and on‐resistance as low as 9 mΩ‐cm 2 for lateral HFET devices on low‐cost silicon substrates. Because of the much larger 2DEG density in lattice‐matched InAlN/GaN HFETs, drain current as high as 2 A/mm was demonstrated, and the highest current gain cutoff frequency of 370 GHz was also reported on 7.5‐nm‐thick In 0.17 Al 0.83 N barrier HFETs. The very low on‐resistance allows high drain current, but it is subject to the junction temperature the devices can tolerate and is also restricted by the thermal expansion mismatch of the GaN‐on‐Si structures. Normally‐on and Normally‐off GaN HFETs with breakdown voltages in the range of 20–900 V are already commercially available. However, their competitivity against Si‐based IGBT and super junction MOSFETs and SiC‐FETs would depend on several factors such as voltage derating (used voltage versus the breakdown voltage), long‐term reliability, and cost. The advent of high‐quality SiGe layers on Si substrates has paved the way for the exploration and exploitation of heterostructure devices in an Si environment. MODFETs based on the Si/SiGe have been achieved with extraordinary p ‐channel performance. With 0.25‐μm gate lengths, the current gain cutoff frequency is about 40 GHz. When the gate length was reduced to 0.1 μm, the current gain cutoff frequency increased to about 70 GHz. MODFETs based on Ga 2 O 3 , especially β‐Ga 2 O 3 , have attracted a good deal of interests by the potential high breakdown voltage of Ga 2 O 3 but suffer from limitations imposed by both low electron mobility (affects efficiency and loss) and low thermal conductivity, hindering heat dissipation.

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Efficient and Accurate Schematic Transistor Model of FinFET Parasitic Elements

Cited by 26 publications

References 6 publications

Modeling of Resistance in FinFET Local Interconnect

Modeling of Resistance in FinFET Local Interconnect

(Invited) Parastic Elements in Gate Stacks and Contacts of Planar and Fin Transistors

Modulation Doped FETs

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