Efficient and Effective Failure Analysis of Low-Resistive Defect in Logic Device Using Layout-aware and Volume Diagnosis

Abstract

Efficient and effective failure analysis (FA) of low-resistive defect was studied by using layout-aware and volume diagnosis. Small or marginal defect is one of the most difficult defectivities to identify during FA effort, especially if defect-induced resistance is not as high as the electrical isolation can detect. Here, we used new analysis methodologies, particularly using layout-aware and volume diagnosis, and prioritizing patterns in terms of a defective risk for following FA. The actual FA work verified that new analysis methodologies successfully identified low-resistive defect of Back-End-of-Line (BEOL) which was not detected by a conventional way and efficiently reduced the turn-around time (TAT) of physical failure analysis (PFA) by 57%, prompting fast feedback to fab.