Efficient architecture/compiler co-exploration using analytical models

Abstract

The hardware/software co-exploration is a critical phase for a broad range of embedded platforms based on the System-On-Chip approach. Traditionally, the compilation and the architectural design sub-spaces have been explored independently. Only recently, some approaches have analyzed the problem of the concurrent exploration of the compilation/architecture sub-spaces. This paper proposes a framework to support the co-exploration phase of the design space composed of architectural parameters and source program transformations. The objective space is multi-dimensional, including conflicting objectives such as energy and delay. In the proposed framework, heuristic co-exploration techniques based on Pareto Simulated Annealing (PSA) have been used to efficiently explore the architecture/compiler co-design space. A first result of this paper consists of showing how the architecture/compiler co-exploration can be more effective than a traditional two-phase exploration. Since the co-exploration space is quite large, to speed up the co-exploration phase by several orders of magnitude over simulation-based approaches, a methodology based on analytical models has been introduced in the co-exploration framework. The goal of analytical models is to quickly evaluate energy/delay metrics at the systems level, while maintaining accuracy with respect to simulation-based co-exploration. The proposed co-exploration framework has been applied to a parameterized SoC superscalar architecture during the execution of a selected set of multimedia applications.

A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs

“…Concerning the exploration of mapping solutions, different techniques have been proposed (e.g., Ferrandi et al, 2010) but without interfacing with real simulations, losing in accuracy. On the other hand, different algorithms have been proposed to efficiently explore the architectural design space (Beltrame et al, 2010, Mariani et al, 2012 and code transformations (Agosta et al, 2007), also in the situation where an actual simulation is required. However, none of these solutions have ever been applied to the mapping problem.…”

“…Besides analytical approaches (Agosta et al, 2007, Ferrandi et al, 2010, based on worst case execution time estimation and static scheduling, the designer may require additional information by means of simulations, at different abstraction levels, especially when the actual platform is not fully implemented. These simulators can consider either SystemC performance models (e.g., Kempf et al, 2005) or slower but more accurate ISS-based Instruction Set Simulators (ISSs) (e.g., Qin & Malik, 2003, Beltrame et al, 2006, Beltrame et al, 2009, Synopsys, 2012.…”

“…In this paper, we focus on the case where the designer desires to perform a simulation of the complete system (i.e., mapped application running on the top of the target architecture) to enable an accurate tuning of the design parameters, both architectural and application's ones. In this scenario, if the exploration of architectural parameters and the application optimization through code transformations have been already addressed by several approaches (Agosta et al, 2007, Beltrame et al, 2010, Mariani et al, 2012, the exploration of mapping solutions presents several issues, especially in the case of hardware accelerators, that have not been fully automated yet. Indeed, in most of the cases, the generation of the models for the hardware accelerators and their interfacing with the rest of the application is manually performed, preventing the possibility of automating the exploration.…”