Efficient CMOL Gate Designs for Cryptography Applications

Abid, Z.; Alma'aitah, Abdallah Y.; Barua, Mrinmoy; Wang, W.

doi:10.1109/tnano.2008.2011812

Cited by 29 publications

(17 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…An Evolutionary Optimization (EO) environment has been developed at UTK to configure the neural networks in a DANNA [1][2][3][4][5][6]. The EO trains over parameters of the network (weights and delay distances on synapses and thresholds on neurons) as well as the structure (the number and placement of neurons and synapses) and the dynamics of the network.…”

Section: Resultsmentioning

confidence: 99%

Multifunctional Nanotechnology Research

Nostrand¹,

Joseph²

2016

View full text Add to dashboard Cite

Section: Resultsmentioning

confidence: 99%

Multifunctional Nanotechnology Research

Nostrand¹,

Joseph²

2016

View full text Add to dashboard Cite

“…The percentage of hardware resources utilized by this module may vary depending on how the S-box is implemented. If the S-box is implemented by combinational logic circuit, XOR gates become the dominant resources, which account for more than 70% of gate utilization for the AES implementation, as reported in [7]. • ShiftRows: The n th row of M s will be cyclically shifted to the left by n bytes.…”

Section: A Preliminary On Advanced Encryption Standardmentioning

confidence: 99%

“…The proposed DW-AES cipher is compared with both CMOS-based ASIC design [4], [6] and hybrid CMOS/ReRAM (CMOL) design [7]. In ASIC implementation, the performance data is extracted from the reported results in [4], [6] with the following technology scaling: Area ∼ 1/S 2 , Delay ∼ 1/S 2 , Energy ∼ 1/S, where S = L/32nm and leakage scaling factor from [36].…”

Section: Aes Performance Comparisonmentioning

confidence: 99%

“…In ASIC implementation, the performance data is extracted from the reported results in [4], [6] with the following technology scaling: Area ∼ 1/S 2 , Delay ∼ 1/S 2 , Energy ∼ 1/S, where S = L/32nm and leakage scaling factor from [36]. The stacked CMOL AES performance is projected from [7]. In particular, the lower layer CMOS gates are evaluated with the aforementioned technology scaling together with the interconnection improvement ratio by the upper non-volatile layer.…”

Section: Aes Performance Comparisonmentioning

confidence: 99%

“…However, CMOS-based ASIC implementations tend to dissipate high static power in current deep sub-micron technology with their speed limited by lowvoltage operation. In [7], a memristive CMOL implementation based on hybrid CMOS and ReRAM is introduced to improve the performance of AES encryption. As the storage device is non-volatile, leakage current is cut-off completely when unused.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory

Wang

Chang

et al. 2016

IEEE Trans.Inform.Forensic Secur.

View full text Add to dashboard Cite

Big-data storage poses significant challenges to anonymization of sensitive information against data sniffing. Not only will the encryption bandwidth be limited by the I/O traffic, the transfer of data between processor and memory will also expose the input-output mapping of intermediate computations on I/O channels that are susceptible to semi-invasive and noninvasive attacks. Limited by the simplistic cell-level logic, existing logic-in-memory computing architectures are incapable of performing the complete encryption process within the memory at reasonable throughput and energy efficiency. In this paper, a block-level in-memory architecture for Advanced Encryption Standard (AES) is proposed. The proposed technique, called DW-AES, maps all AES operations directly to the domainwall nanowires. The entire encryption process can be completed within a homogeneous, high-density and standby-power-free non-volatile spintronic based memory array without exposing the intermediate results to external I/O interface. Domain-wall nanowires based pipelining and multi-issue pipelining methods are also proposed to increase the throughput of the baseline DW-AES with insignificant area overhead and negligible difference on leakage power and energy consumption. The experimental results show that DW-AES can reduce the leakage power and area by orders of magnitude compared to existing CMOS ASIC accelerators. It has an energy efficiency of 22 pJ/bit, which is 5× and 3× better than the CMOS ASIC and memristive CMOL based implementations, respectively. Under the same area budget, the proposed DW-AES achieves 4.6× higher throughput than the latest CMOS ASIC AES with similar power consumption. The throughput improvement increases to 11× for pipelined DW-AES at the expense of doubling the power consumption.

show abstract

Nonvolatile Memory Computing System

Wang

2014

Design Exploration of Emerging Nano-Scale Non-Volatile Memory

View full text Add to dashboard Cite

Efficient CMOL Gate Designs for Cryptography Applications

Cited by 29 publications

References 8 publications

Multifunctional Nanotechnology Research

Multifunctional Nanotechnology Research

DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory

Nonvolatile Memory Computing System

Contact Info

Product

Resources

About