Efficient coarse frequency synchronizer using serial correlator for DVB-S2

Park, Jang Woong; Yun, Hyoung Jin; Sunwoo, Myung Hoon; Kim, Pansoo; Chang, Dae-Ig

doi:10.1109/iscas.2008.4541719

Cited by 8 publications

(7 citation statements)

References 7 publications

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“…Since the accuracy of the M&M algorithm is better than that of the L&W algorithm [5] and its estimation range is larger than the other algorithms [4][5][6], we employ the M&M algorithm in our previous work [5].…”

Section: Frequency Synchronization Algorithmsmentioning

confidence: 99%

“…Fig. 1 depicts the existing hardware architecture [4][5][6]. In the existing architecture, each synchronization block can be independently operated since they are designed in serial.…”

Section: Proposed Hardware Architecturementioning

confidence: 99%

“…To overcome this problem, more sophisticated and efficient algorithms should be employed for the frame synchronization and carrier frequency synchronization. To reach the requirement, we intend to use the Differential -Generalized Post Detection Integration (D-GPDI) algorithm for the frame synchronization and the Mengali and Moreli (M&M) algorithm for the carrier frequency synchronization [4][5][6]. Since these algorithms are based on Maximum Likelihood (ML) method, they contain autocorrelation operations.…”

Section: Introductionmentioning

confidence: 99%

“…Since these algorithms are based on Maximum Likelihood (ML) method, they contain autocorrelation operations. However, the complexity of autocorrelators is so high since autocorrelation operations should be carried out through the complex multiplications of 26 Start Of Frame (SOF) symbols and the existing serial architecture [6] may be inefficient in terms of robust algorithm design and hardware complexity. With this rationale, to reduce high hardware complexity and to achieve suitable performance, we propose an efficient synchronizer architecture which can be jointly used with the common autocorrelator.…”

Section: Introductionmentioning

confidence: 99%

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Low Complexity Synchronizer Using Common Autocorrelator for DVB-S2 System

Park¹,

Sunwoo

Kim³

et al. 2009

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents an efficient synchronizer architecture using a common autocorrelator for Digital Video Broadcasting via Satellite, Second generation (DVB-S2). To achieve the required performance under the worst channel condition and to implement the efficient H/W resource utilization of functional synchronization blocks, we propose a new efficient common autocorrelator structure. The proposed architecture can decrease about 92% of multipliers and 81% of adders compared with the direct implementation. Moreover, the proposed architecture has been thoroughly verified in XilinxTM Virtex IV and R&STM SFU (Signaling and Formatting Unit) broad-cast test equipment.

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Section: Frequency Synchronization Algorithmsmentioning

confidence: 99%

“…Fig. 1 depicts the existing hardware architecture [4][5][6]. In the existing architecture, each synchronization block can be independently operated since they are designed in serial.…”

Section: Proposed Hardware Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Low Complexity Synchronizer Using Common Autocorrelator for DVB-S2 System

Park¹,

Sunwoo

Kim³

et al. 2009

JSTS:Journal of Semiconductor Technology and Science

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show abstract

“…Even the variations of this algorithm, that aim to reduce the frequency residue, keep a hardware complexity similar to the original. Several approaches are proposed to reduce the hardware complexity, such as those presented in [122], [123]. In this thesis I propose a new serial architecture to implement the modified L&R algorithm [106] that meets the normalized residual frequency offset required by DVB-S2, with a considerable reduction of hardware complexity.…”

Section: The Proposed Dvb-s2 Receiver Architecture and Algorithmsmentioning

confidence: 99%

Architecture and algorithms for the implementation of digital wireless receivers in FPGA and ASIC: ISDB-T and DVB-S2 cases

Lima¹

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Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator

Savvopoulos

Παπανδρεου

Antonakopoulos

2009

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

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Abstract-This paper presents the design and implementation of a baseband demodulator for DVB-S2 satellite receivers. In order to meet the requirements of different complex and multidomain signal processing stages of the DVB-S2 baseband signalflow, the presented architecture is based on efficient fixed-point implementation of the various demodulation algorithms and on the use of a dynamic time-sharing scheduler for the various DSP software tasks. The prototyping of the demodulator and its verification in the design of a complete digital DVB-S2 satellite receiver using a versatile testbed is also presented.

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Efficient coarse frequency synchronizer using serial correlator for DVB-S2

Cited by 8 publications

References 7 publications

Low Complexity Synchronizer Using Common Autocorrelator for DVB-S2 System

Low Complexity Synchronizer Using Common Autocorrelator for DVB-S2 System

Architecture and algorithms for the implementation of digital wireless receivers in FPGA and ASIC: ISDB-T and DVB-S2 cases

Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator

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