Efficient Compilation for Application Specific Instruction set DSP Processors with Multi-bank Memories

Abstract

Modern signal processing systems require more and more processing capacity as times goes on. Previously, large increases in speed and power efficiency have come from process technology improvements. However, lately the gain from process improvements have been greatly reduced.Currently, the way forward for high-performance systems is to use specialized hardware and/or parallel designs.Application Specific Integrated Circuits (ASICs) have long been used to accelerate the processing of tasks that are too computationally heavy for more general processors. The problem with ASICs is that they are costly to develop and verify, and the product life time can be limited with newer standards. Since they are very specific the applicable domain is very narrow.More general processors are more flexible and can easily adapt to perform the functions of ASIC based designs. However, the generality comes with a performance cost that renders general designs unusable for some tasks. The question then becomes, how general can a processor be while still being power efficient and fast enough for some particular domain?Application Specific Instruction set Processors (ASIPs) are processors that target a specific application domain, and can offer enough performance with power efficiency and silicon cost that is comparable to ASICs.The flexibility allows for the same hardware design to be used over several system designs, and also for multiple functions in the same system, if some functions are not used simultaneously.iii iv One problem with ASIPs is that they are more difficult to program than a general purpose processor, given that we want efficient software.Utilizing all of the features that give an ASIP its performance advantage can be difficult at times, and new tools and methods for programming them are needed.This thesis will present ePUMA (embedded Parallel DSP platform with Unique Memory Access), an ASIP architecture that targets algorithms with predictable data access. These kinds of algorithms are very common in e.g. baseband processing or multimedia applications. The primary focus will be on the specific features of ePUMA that are utilized to achieve high performance, and how it is possible to automatically utilize them using tools. The most significant features include data permutation for conflict-free data access, and utilization of address generation features for overhead free code execution. This sometimes requires specific information; for example the exact sequences of addresses in memory that are accessed, or that some operations may be performed in parallel. This is not always available when writing code using the traditional way with traditional languages, e.g. C, as extracting this information is still a very active research topic. In the near future at least, the way that software is written needs to change to exploit all hardware features, but in many cases in a positive way. Often the problem with current methods is that code is overly specific, and that a more general abstractions are actually easier to ge...

Design of Energy-Efficient High-Performance ASIP-DSP Platforms

“…The performance gained by using multi-bank memory has been demonstrated in many other publications, such as [38]. The relative speed-up by switching to multi-bank memory may approach P for algorithms such as FFT [8]. …”

“…The system-level design and network-on-chip is presented in [7]. Software-related aspects are detailed in [8]. This thesis primarily focuses on the processor core-level design and core-level toolchain issues.…”

“…For example, a P -way architecture will require permutation tables of size c · P, c ∈ N, to maximize processor utilization and therefore there is no upper bound on the required permutation table size. A better practical solution is possibly to formulate the data access pattern in a processing width independent way, and then generate/compile code for the current width, since the generation of a permutation table for a given processing width can be performed automatically [8].…”

“…In case padding is not satisfactory, one can turn to general permutation, which may improve dynamic memory usage density, but increases the size of permutation tables. In this case, it is typically beneficial to divide a larger data structure into blocks, blocks which have side lengths of the processing width P or a multiple thereof [46,8].…”

“…Previous work regarding kernel programming of the ePUMA MPE include the FT language and its compiler [8]. The main purpose was to demonstrate how the 2D addressing features of the MPE could be applied automatically, through the use of dataflow analysis [124].…”