Efficient continual learning at the edge with progressive segmented training

Abstract

There is an increasing need for continual learning in dynamic systems at the edge, such as self-driving vehicles, surveillance drones, and robotic systems. Such a system requires learning from the data stream, training the model to preserve previous information and adapt to a new task, and generating a single-headed vector for future inference, within a limited power budget. Different from previous continual learning algorithms with dynamic structures, this work focuses on a single network and model segmentation to mitigate catastrophic forgetting problem. Leveraging the redundant capacity of a single network, model parameters for each task are separated into two groups: one important group which is frozen to preserve current knowledge, and a secondary group to be saved (not pruned) for future learning. A fixed-size memory containing a small amount of previously seen data is further adopted to assist the training. Without additional regularization, the simple yet effective approach of Progressive Segmented Training (PST) successfully incorporates multiple tasks and achieves state-of-the-art accuracy in the single-head evaluation on the CIFAR-10 and CIFAR-100 datasets. Moreover, the segmented training significantly improves computation efficiency in continual learning and thus, enabling efficient continual learning at the edge. On Intel Stratix-10 MX FPGA, we further demonstrate the efficiency of PST with representative CNNs trained on CIFAR-10.

Editorial: Focus on algorithms for neuromorphic computing

“…For learning at the edge, where the artificial system should continually adapt to the sensory data stream in changing situations, continual learning capabilities are essential. Du et al [3] propose a simple yet effective approach of progressive segmented training for continual learning in a single network. Moreover, their training approach significantly improves computational efficiency, enabling efficient continual learning at the edge which is demonstrated on an FPGA platform.…”