Efficient design of 32-bit comparator using carry look-ahead logic

High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule

“…We have suggested a carry look-ahead adder (CLA) based comparison scheme that results in path delay. The effectiveness of using CLA for comparison has been reported in previous works like [20]. Fig.…”

A High Performance Unified BCD and Binary Adder/Subtractor

“…Humberto's Proposal [12] Sreehari et al [9] recently came up with the prefix logic based BCD adders and proposed a novel unified BCD binary adder-subtractor [10] which is considered as the fastest unified adder in the literature so far. The architecture is divided into three major parts, the pre-computation stage, the prefix network and the post-computation stage.…”

“…The pre-computation block consists of logic to compute propagate and generate signals for both BCD and Binary addition/subtraction. Adder/Subtractor [10] The pre-computation stage of the architecture is not clearly presented by the authors in the paper [10] and it is assumed that they have used the same P-G block presented in [9]. The P-G block uses a Carry Merge block, CM (as shown in Fig.6), which is used for group propagate and generate.…”

“…The post-computation block proposed by Sreehari et al [10] (Fig. 7) uses a 4 bit CLA to add the two numbers to calculate the sum/difference and the carry out bits for each stage.…”

“…The P and G for a stage denote whether the stage propagates or generates the carry/borrow respectively. Along with generating these signals, the sum/difference of the 4 bit numbers is obtained that is directly used by the correction logic unlike the previous design [10]. The P-G block itself uses prefix logic to generate the P and G signals for 4 bit numbers.…”