Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior

Giustolisi, G.; Palumbo, G.

doi:10.3390/electronics10050612

Cited by 5 publications

(4 citation statements)

References 35 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Among the various possibilities, settinĝ K e =K i = 2 turns the denominator of the closed-loop transfer function into a third-order Butterworth polynomial with a cut-off frequency ω 0 = 2 GBW/(1 + b 1 GBW). In similar fashion, as demonstrated in [62], settingK e = 8/3 andK i = 9/4 optimizes the step response of the OTA, since it minimizes the settling time for a given GBW.…”

Section: Small-signal Analysis and Stability Requirementsmentioning

confidence: 91%

“…The small-signal settling time, t s0 , depends on the GBW of the amplifier and on the values of the global separation factors,K e andK i . As demonstrated in [62], choosinĝ K e = 8/3 andK i = 9/4 makes the small-signal settling time lower than that of a singlepole amplifier with the same GBW. In other words, under small-signal condition, the amplifier settles in t s0 ≤ | ln |/GBW and, to our purposes, (20) can be simplified into:…”

Section: Settling Time Slew Rate and Gain-bandwidth Productmentioning

confidence: 97%

“…The stability of the amplifier can be achieved using the global separation factors introduced in [60] and used in [61,62]. Without going into theoretical detail, our three-stage OTA can be considered as a feedback circuit with two nested loops, each of which must be frequency compensated.…”

Section: Small-signal Analysis and Stability Requirementsmentioning

confidence: 99%

See 2 more Smart Citations

A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

Giustolisi

Palumbo

2021

JLPEA

Self Cite

View full text Add to dashboard Cite

In this paper, a new strategy for the design of ultra-low-power CMOS operational transconductance amplifiers (OTAs), using the gm/ID approach, is proposed for the Internet-of-things (IoT) scenario. The strategy optimizes the speed/dissipation of the OTA in terms of settling time, including slew-rate effects. It was designed for large capacitive loads and for transistors biased in the sub-threshold region, but it is also suitable for low-capacitive loads or for transistors biased in the saturation region. To validate the proposed strategy, a well-known three-stage OTA was designed starting from capacitive load and settling time requirements. Simulations confirmed that the OTA satisfies the specifications (even under Monte Carlo analysis), thus proving the correctness of the proposed approach.

show abstract

Section: Small-signal Analysis and Stability Requirementsmentioning

confidence: 91%

Section: Settling Time Slew Rate and Gain-bandwidth Productmentioning

confidence: 97%

See 1 more Smart Citation

A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

Giustolisi

Palumbo

2021

JLPEA

Self Cite

View full text Add to dashboard Cite

show abstract

“…As stated in [16][17][18][19], the design of 3-stage OTAs is best approached in the time domain. With the target application in mind, we note that a 20 MHz signal has a period of 50 ns.…”

Section: Performance Specificationsmentioning

confidence: 99%

Design Trade-Offs in Common-Mode Feedback Implementations for Highly Linear Three-Stage Operational Transconductance Amplifiers

et al. 2021

View full text Add to dashboard Cite

Fully differential amplifiers require the use of common-mode feedback (CMFB) circuits to properly set the amplifier’s operating point. Due to scaling trends in CMOS technology, modern amplifiers increasingly rely on cascading more than two stages to achieve sufficient gain. With multiple gain stages, different topologies for implementing CMFB are possible, whether using a single CMFB loop or multiple ones. However, the impact on performance of each CMFB approach has seldom been studied in the literature. The aim of this work is to guide the choice of the CMFB implementation topology evaluating performance in terms of stability, linearity, noise and common-mode rejection. We present a detailed theoretical analysis, comparing the relative performance of two CMFB configurations for 3-stage OTA topologies in an implementation-agnostic manner. Our analysis is then corroborated through a case study with full simulation results comparing the two topologies at the transistor level and confirming the theoretical intuition. An active-RC filter is used as an example of a high-linearity OTA application, highlighting a 6 dB improvement in P1dB in the multi-loop implementation with respect to the single-loop case.

show abstract

Exact Settling Performance Design for CMOS Three-Stage Nested-Miller-Compensated Amplifiers

Wang

Yu-shun

Zhang

et al. 2022

Circuits Syst Signal Process

View full text Add to dashboard Cite

Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior

Cited by 5 publications

References 35 publications

A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

Design Trade-Offs in Common-Mode Feedback Implementations for Highly Linear Three-Stage Operational Transconductance Amplifiers

Exact Settling Performance Design for CMOS Three-Stage Nested-Miller-Compensated Amplifiers

Contact Info

Product

Resources

About