Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources

Feilen, Michael; Ihmig, Matthias; Schwarzbauer, Christian; Stechele, Walter

doi:10.1109/fpl.2012.6339244

Cited by 7 publications

(2 citation statements)

References 8 publications

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“…FPGA resources sharing is a requirement and promising technique to reuse resources for different configuration circuits. Feilen et al proposed to switch between signal processing DVB-T2 tasks in a time multiplexed by using DPR [12]. To share circuit-specific DSP blocks from Xilinx, the authors described that multiple sets of DSP blocks are controlled by state machines to ensure that each set achieves a high initiation interval instead of reconfiguring a set of DSP blocks to implement all operations [13].…”

Section: Overlays For High Productivity and Portabilitymentioning

confidence: 99%

A SLM-based overlay architecture for fine-grained virtual FPGA

Myint

Amagasaki

Zhao

et al. 2019

IEICE Electron. Express

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FPGA overlay technologies have been introduced to provide inter-FPGA bitstream compatibility by implementing virtual FPGA (vFPGA) layers on physical devices. Conventional LUT-based fine-grained vFPGAs have very large resource overheads. In this paper, we propose a fine-grained vFPGA overlay architecture that employs our previously proposed scalable logic module (SLM) as a logic cell. SLMs can cover most frequently used logics with far fewer hardware resources than LUTs. Evaluation results show that a 7-input SLM-based vFPGA can reduce LUT and flip-flop resource usage by up to 32% and 35% on an Artix-7 FPGA, 30% and 35% on a Kintex-7 FPGA, and 30% and 35% on a Kintex UltraScale+ FPGA respectively, as compared to a LUT-based vFPGA of the same input size.

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Section: Overlays For High Productivity and Portabilitymentioning

confidence: 99%

A SLM-based overlay architecture for fine-grained virtual FPGA

Myint

Amagasaki

Zhao

et al. 2019

IEICE Electron. Express

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“…For instance, in [1], [2], [3], partial reconfiguration was used for adapting systems to environmental changes (e.g., light conditions in a vision system or channel quality in a wireless communication system). As the environment can only be in one specific state, specialized hardware accelerators were used for adapting a system at run-time.…”

Section: Introductionmentioning

confidence: 99%

Hierarchical reconfiguration of FPGAs

Koch

Beckhoff

2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-Partial reconfiguration allows some applications to substantially save FPGA area by time sharing resources among multiple modules. In this paper, we push this approach further by introducing hierarchical reconfiguration where reconfigurable modules can have reconfigurable submodules. This is useful for complex systems where many modules have common parts or where modules can share components. For such systems, we show that the number of bitstreams and the bitstream storage requirements can be scaled down from a multiplicative to an additive behavior with respect to the number of modules and submodules. A case study consisting of different reconfigurable softcore CPUs and hierarchically reconfigurable custom instruction set extensions demonstrates a 18.7× lower bitstream storage requirement and up to 10× faster reconfiguration speed when using hierarchical reconfiguration instead of using conventional single-level module-based reconfiguration.

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Reconfigurable Computing

Boland

Chung-Kuan

Kahng

et al. 2017

Wiley Encyclopedia of Electrical and Electronics Engineering

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Reconfigurable computing is the application of adaptable fabrics to address computational problems, often taking advantage of the flexibility of field‐programmable gate arrays (FPGAs) to produce problem‐specific solutions. It has been successfully applied to fields as diverse as machine learning, digital signal processing, cryptography, bioinformatics, logic emulation, CAD tool acceleration, scientific computing, and rapid prototyping.In this article, intended for the nonspecialist, we describe some of the basic concepts, tools, and architectures associated with reconfigurable computing.

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Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources

Cited by 7 publications

References 8 publications

A SLM-based overlay architecture for fine-grained virtual FPGA

A SLM-based overlay architecture for fine-grained virtual FPGA

Hierarchical reconfiguration of FPGAs

Reconfigurable Computing

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