Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems

Oveis-Gharan, Masoud; Khan, Gul N.

doi:10.1109/tvlsi.2015.2405933

Cited by 31 publications

(8 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Efficient Dynamic Virtual Channel (EDVC) organization and its novel features are discussed in Chapter 4 [54,59]. A 4-slot EDVC input-port consumes on average 10% less registers, 61%…”

Section: Discussionmentioning

confidence: 99%

See 1 more Smart Citation

Virtual channel organization and arbitration for network on chip router architecure

Gharan¹

2021

Preprint

View full text Add to dashboard Cite

The advent of Multi-Processor Systems-on-Chip (MPSoC) has emphasized the importance of on-chip communication infrastructures. Network on Chip (NoC) has emerged as a state of the art paradigm for efficient on-chip communication. Among the various components employed in NoC routers, Virtual Channel (VC) plays an important role in the performance and hardware requirements of an NoC system. The VC mechanism enables the multiplexing and buffering of several packets to travel over a single physical channel concurrently. VC arbitration (or arbiter) is another critical organization component of a router that has significant impact on the efficiency of an NoC system. Arbiter performs arbitration among the group of VCs that are competing for a single resource (e.g. output-port). In this dissertation, we propose novel approaches for dynamic VC flow control mechanism and VC arbitration. The first two approaches are based on the adaptivity of VCs in the router input-port that improves the efficiency of NoC system. In both of techniques, the input-port comprises of a centralized buffer whose slots are dynamically allocated to VCs according to a real-time traffic situation. The performance improvement is achieved by utilizing multiple virtual channels with minimal buffer resources. The VC arbitration approach is based on an efficient and fast arbiter that functions upon the index of its input-ports (or VC requests). The architecture of arbiter scales with the Log2 of the number of inputs where a conventional round robin arbiter scales with the number of inputs. The index based behavior and the architecture of our arbiter leads to lower power consumption and chip area. This dissertation presents the organizations and micro-architectures of NoC routers. We have employed SystemVerilog at the micro-architectural level design and modeling of NoC components. We employ three CAD platforms namely ModelSim, Quartus (FPGA) and Synopsys (ASIC level) to design, simulate and implement our router based NoCs. The simulation results support the theoretical concepts of our proposed VC organization and arbitration approaches. We have also implemented and conducted simulation and modeling experiments for conventional VC organization and arbitration models. The experimental results verify the efficiency of our proposed models in terms of power, area and performance in different NoC configurations.

show abstract

“…Efficient Dynamic Virtual Channel (EDVC) organization and its novel features are discussed in Chapter 4 [54,59]. A 4-slot EDVC input-port consumes on average 10% less registers, 61%…”

Section: Discussionmentioning

confidence: 99%

“…In the first experiment, we simulated and tested EDVC mechanism for two different traffic patterns including Application-Specific and Hotspot traffic patterns [53,54]. For Application-Specific traffic, two NoC applications presented in Section 3.…”

Section: ) Application Specific and Hotspot Traffic Patternsmentioning

confidence: 99%

Virtual channel organization and arbitration for network on chip router architecure

Gharan¹

2021

Preprint

View full text Add to dashboard Cite

show abstract

“…We will be using a library of pre-synthesized NoC router components and information about application (CoreGraph) to optimize these metrics. The architecture of these pre-synthesized router components are discussed by Oveis-Gharan and Khan [2,3,4,5,6,7]. These pre-synthesized components are imported into our tool and their power and area metrics are presented in Section 4.10.1.…”

Section: List Of Figuresmentioning

confidence: 99%

Application mapping and NoC configuration using hybrid particle swarm optimization

Obaidullah¹

2021

Preprint

View full text Add to dashboard Cite

Network-on-Chip (NoC) has been proposed as an interconnection framework for connecting large number of cores for a System-on-Chip (SoC). Assuming a mesh-based NoC, we investigate application mapping and NoC configuration optimization using a hybrid optimization scheme. Our technique, Hybrid Discrete Particle Swarm Optimization (HDPSO), combines Tabu-search, communication volume based core swapping, and swarm intelligence. We employ a Tabu-list to discourage swarm particles to re-visit the explored search space and propose an alternative route towards the intended movement direction. In each iteration of swarm, a sub-swarm containing configuration solutions (sub-particles) searches for optimal configuration for the parent particle (mapping solution). Optimization goals include minimum average communication latency, power, area, credit loop latency, and maximum average link duty factor. The proposed technique is tested for well-known multimedia application core graphs and several large synthetic cores-graphs. It was found that on average our hybrid scheme generates high quality NoC mapping and configuration solutions when compared to some existing stochastic optimization techniques.

show abstract

“…Gharan and Khan [15] have presented a dynamic VC organization and architecture for NoC systems. They proposed an input-port micro-architecture to support a dynamic virtual channel.…”

Section: Router Architecture With Shared Queuesmentioning

confidence: 99%

A Routing Algorithm and a Router Architecture for 3d Noc

Somasundaram

Calicut

2019

csci

View full text Add to dashboard Cite

In recent years, the enhancement of microchip technologies has enabled large scale Systems-on-Chip (SoC). Due to sharp increase in number of processing elements, SoC faces various challenges in design and testing. Network on Chip (NoC) is an alternative technology to overcome the challenges in SoC design and testing. NoC emerged as a key architecture that allows one to optimize the parameters like power andarea. Inspiteofitsapplications, NoCfacessomerealtimechallengeslikedesigning an optimum topology, routing scheme and application mappings. In this paper, we address the main three issues on NoC, namely, designing of an optimal topology, routing algorithm and a router design for the topology. First, we propose a topology and a routing algorithm. We prove that our recursive network topology is Hamiltonian connected and we propose an algorithm for data packet transmissions, which is free from cyclic deadlocks and the algorithm maximizes the congestion factor. Our experimental results show that the proposed topology gives better performance in terms of average latency and power than the other topologies. Finally, we propose a router architecture for our 3D-NoC. The router architecture is based on shared buffers. Also, our experimental results indicate that the proposed router architecture consumes less area and power than the Virtual Channel architecture.

show abstract

Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems

Cited by 31 publications

References 19 publications

Virtual channel organization and arbitration for network on chip router architecure

Virtual channel organization and arbitration for network on chip router architecure

Application mapping and NoC configuration using hybrid particle swarm optimization

A Routing Algorithm and a Router Architecture for 3d Noc

Contact Info

Product

Resources

About