Efficient FPGA Implementations of Point Multiplication on Binary Edwards and Generalized Hessian Curves Using Gaussian Normal Basis

Azarderakhsh, Reza; Reyhani-Masoleh, Arash

doi:10.1109/tvlsi.2011.2158595

Cited by 70 publications

(54 citation statements)

References 41 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Our state of art achieves double the speed of [11] but consuming only 25 % more slices. The presented work in [17] consumes 6536 slices to get a speed of 12.9 µs; our area-time metric is 3.81 times better than that in [17].…”

Section: Implementation Resultsmentioning

confidence: 92%

“…If the field squaring and field addition operations can be operated concurrently with multiplication then the point operations latency will be equivalent to the latency of the six field multiplications. The six multiplications can, for example, be computed in two steps using three multipliers or in three steps using two multipliers or in six steps by serial multiplications using one multiplier [17], [13] and [10]. Again, the digit size can affect the performance of ECC; for example, a bit serial implementation takes m cycles, a digit ( bits) serial one takes ( / ) cycles and a bit parallel implementation takes a single clock cycle [8], [12] and [11].…”

Section: A Point Multiplication Without Pipelining Delaymentioning

confidence: 99%

“…Many high performance ECC processor implementations on FPGA have been reported in the literature; the most relevant are presented in [10], [11], [12], [13], [14], [15], [16], [17], [20], [21], [22], and [23]. The common optimizing technique of high speed designs is the reduction of latency (number of clock Z. U.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Khan

Benaïssa

2017

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-In this paper, a novel high speed ECC processor implementation for point multiplication on Field Programmable Gate Array (FPGA) is proposed. A new segmented pipelined fullprecision multiplier is used to reduce the latency and the LopezDahab (LD) Montgomery point multiplication algorithm is modified for careful scheduling to avoid data dependency resulting in a drastic reduction in the number of clock cycles required. The proposed ECC architecture has been implemented on Xilinx FPGAs Virtex4, Virtex5 and Virtex7 families. To our knowledge, our single multiplier and three multipliers based designs show the fastest performance to date when compared to reported works individually. Our one multiplier based ECC processor also achieves the highest reported speed together with the best reported area-time performance on Virtex4 (5.32 µs at 210 MHz), on Virtex5 (4.91 µs at 228 MHz), and on the more advanced Virtex7, (3.18 µs at 352 MHz). Finally, the proposed three multiplier based ECC implementation is the first work reporting the lowest number of clock cycles and the fastest ECC processor design on FPGA (450 clock cycles to get 2.83 µs on Virtex7).

show abstract

Section: Implementation Resultsmentioning

confidence: 92%

Section: A Point Multiplication Without Pipelining Delaymentioning

confidence: 99%

See 1 more Smart Citation

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Khan

Benaïssa

2017

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…The controller is designed as a finite state machines (FSM) to perform point multiplication. The register file holds the values of the base point We implemented the presented multiplier in [9], which is based on [10,17], over GFð2 163 Þ with two digit sizes = 33 and 41, for fair comparison. In a digit-level parallel-in parallel-out GNB multiplier, the results are available in parallel after q ¼ dm=de clock cycles, where d is the digit size.…”

Section: Implementation and Resultsmentioning

confidence: 99%

“…Binary curves have attracted many researchers to reduce point multiplication. These methods include parallelization, by using multiple parallel field multipliers in the finite field computations [8,9,10,11], and by interleaving [12,13]. Recently, several methods to perform parallel computations for point addition on Koblitz curves have been proposed in [8,9,11,13,14,15].…”

Section: Introductionmentioning

confidence: 99%

Very efficient point multiplication on Koblitz curves

Al-Somani

2016

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents a very efficient scheme for point multiplication on Koblitz curves. The proposed scheme reduces the critical path in the data dependency graph of the point addition operation and increases the utilization of the three parallel multipliers that are used. The proposed scheme exploits an idle multiplier to perform an extra field operation that will be needed in the next iteration. Furthermore, the proposed scheme is implemented on an Altera Stratix II EP2S180F1020C3 FPGA over GF (2 163 ) and compared with the related parallel schemes in the literature. The results show that the proposed scheme outperforms the previous schemes in terms of the area-time (AT) and AT 2 products. Accordingly, the proposed scheme is very attractive for use in high-performance applications.

show abstract

Efficient hardware implementations of point multiplication for binary Edwards curves

Rashidi

2018

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryThis paper presents efficient and fast hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on extremely fast complete differential addition and doubling formulas. These new complete differential addition formulas are performed for general and special cases of BECs with cost of 5M + 4S + 2D and 5M + 4S + 1D, respectively, where, M, S, and D denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of the BECs, proposed structures are implemented based on 3 and 1 pipelined digit‐serial Gaussian normal basis multipliers. In the design by 3 multipliers, computation of point addition and point doubling is performed concurrently. But in the second implementation for low‐cost design with low number of hardware resources, these computations are implemented by 1 multiplier. Also, in the special case of BECs, 2 structures are proposed for achieving the highest degree of parallelization and utilization of resources by using 3 and 2 field multipliers. Implementation results of the proposed architectures based on Virtex‐5 XC5VLX110, Virtex‐4 XC4VLX100, and Arria‐10 10AX115U4F45I3SG FPGAs for 2 fields and are achieved. The results show improvements in terms of execution time, area, and efficiency for the proposed structures compared with previous works.

show abstract

Efficient FPGA Implementations of Point Multiplication on Binary Edwards and Generalized Hessian Curves Using Gaussian Normal Basis

Cited by 70 publications

References 41 publications

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Very efficient point multiplication on Koblitz curves

Efficient hardware implementations of point multiplication for binary Edwards curves

Contact Info

Product

Resources

About