Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography

Abstract

Ring learning-with-errors (RLWE)-based encryption scheme is a lattice-based cryptographic algorithm that constitutes one of the most promising candidates for Post-Quantum Cryptography (PQC) standardization due to its efficient implementation and low computational complexity. Binary Ring-LWE (BRLWE) is a new optimized variant of RLWE, which achieves smaller computational complexity and higher efficient hardware implementations. In this paper, two efficient architectures based on Linear-Feedback Shift Register (LFSR) for the arithmetic used in Inverted Binary Ring-LWE (InvBRLWE)-based encryption scheme are presented, namely the operation of A • B + C over the polynomial ring Z q /(x n + 1). The first architecture optimizes the resource usage for major computation and has a novel input processing setup to speed up the overall processing latency with minimized input loading cycles. The second architecture deploys an innovative serial-in serial-out processing format to reduce the involved area usage further yet maintains a regular input loading time-complexity. Experimental results show that the architectures presented here improve the complexities obtained by competing schemes found in the literature, e.g., involving 71.23% less areadelay product than recent designs. Both architectures are highly efficient in terms of area-time complexities and can be extended for deploying in different lightweight application environments.

KINA: Karatsuba Initiated Novel Accelerator for Ring-Binary-LWE (RBLWE)-based Post-Quantum Cryptography

“…chosen the same parameter settings according to the existing designs of [23], [24], [29]- [31], i.e., (n, q) = (256, 256) and (n, q) = (512, 256) ( q = 8), which correspond to the quantum/classic security of 73/84-bits and 140/190-bits, respectively [20]; (iv) for a fair and practical comparison, we set the input/output of the proposed accelerator as serialin/serial-out format; (v) the proposed accelerator also includes the third and fourth polynomials Z and W for operations of both encryption and decryption phases as well as related resources; (vi) for a more general demonstration, we do not use the other available resources on the FPGA devices such as the block RAM (BRAM), etc. ; (vii) we have chosen u = 1, u = 2, u = 4, u = 8, and u = 16 for the proposed KINA, respectively, to showcase the high-speed operational performance under different processing setups; (viii) the obtained area-time complexities, in terms of the number of Lookup table (LUT), maximum frequency (Fmax, MHz), latency cycles, delay (critical-path×latency cycles), area-delay product (ADP), and throughput are all listed in Table II along with those of [23], [24], [29]- [31]. Note that the designs of [27], [30] are reported on the Intel Straix-V device and another design of [31] has outperformed them in [31] (thus we do not list [27], [30] here).…”

“…; (vii) we have chosen u = 1, u = 2, u = 4, u = 8, and u = 16 for the proposed KINA, respectively, to showcase the high-speed operational performance under different processing setups; (viii) the obtained area-time complexities, in terms of the number of Lookup table (LUT), maximum frequency (Fmax, MHz), latency cycles, delay (critical-path×latency cycles), area-delay product (ADP), and throughput are all listed in Table II along with those of [23], [24], [29]- [31]. Note that the designs of [27], [30] are reported on the Intel Straix-V device and another design of [31] has outperformed them in [31] (thus we do not list [27], [30] here). Discussion.…”

“…After the initial introduction [22], the authors reported the software implementation work on Atmel-AVR and ARM-Cortex-M0 microcontrollers. While on the hardware platform: (i) the first hardware implementation of the RBLWE-based scheme was released in [23]; (ii) the second hardware design for RBLWE-based PQC was reported in [24]; (iii) a high-speed hardware structure (but incomplete) was then reported in [25]; (iv) a compact RBLWE-based hardware architecture was presented in [26]; (v) a lookup-table (LUT)like method based hardware architecture was reported in [27]; (vi) another compact structure for RBLWE-based PQC was presented in [28]; (vii) a new high-speed hardware RBLWEbased structure was introduced in [29]; (viii) a pair of lowspeed and high-speed RBLWE-based hardware accelerators were presented in [30]; (ix) efficient hardware RBLWE-based architectures were also recently reported in [31], [32], respectively. Meanwhile, there also exist other types of implementations like the fault-resistant (software implementation) one of [33] and the fault detection scheme of [34] (based on the high-speed structure in [24]).…”

Post-Quantum Blockchain-Based Secure Service Orchestration in Multi-Cloud Networks

“…Therefore, there is currently no post-quantum blockchain algorithm that offers fast and small key size, short signature size, low In parallel with these developments, NIST has recently identified four algorithms that are candidates for standardization and will be implemented for most use cases * : CRYSTALS-KYBER (for key-establishment), CRYSTALS-Dilithium (for digital signatures) and FALCON and SPHINCS+ (for signature schemes). There are various forms of implementation concepts for PQC algorithms [17], [18], [19]. For example, in [17], the authors used a PQC algorithm with the Internet of Things (IoT) system from AirBox to monitor air quality in a integration setup demo.…”

Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography

“…Ring-Binary-Learning-with-Errors (RBLWE, a variant of Ring-LWE)-based scheme is a promising PQC to serve such a role as it uses binary errors to obtain small computational complexity. Several related works have recently been carried out on this PQC scheme [3][4][5][6][7][8].…”