Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping

Le, Khoa; Ghaffari, Fakhreddine; Declercq, David; Vasić, Bane

doi:10.1109/tcsi.2016.2633581

Cited by 28 publications

(20 citation statements)

References 17 publications

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“…Unlike the GDBF in which the VNs that satisfy flipping condition are automatically flipped, all the flipping candidates in PGDBF are only flipped with a probability of p (0 < p < 1). Interestingly, this probabilistic behavior improves the decoding performance, far better than the original GDBF and very close to MS [14]. The evolution of BF performance improvement is shown in Fig.…”

Section: Introductionmentioning

confidence: 85%

“…This truly helps the MBF avoid VN miss-flipping and offers a considerable improvement in error correction. The GDBF and PGDBF implementations can be found in [14] and MBF is implemented in [11]. A drawback of these BF decoders is that a global operation (the Maximum Finder -MF in [14] and N-to-4 sorter in [11]) is required to identify the maximum among the VN energy values.…”

Section: Introductionmentioning

confidence: 99%

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A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes

Ghaffari

Kessal

et al. 2019

IEEE Trans. Circuits Syst. I

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This paper presents a new Bit Flipping (BF) decoder, called the Probabilistic Parallel Bit Flipping (PPBF) for Low-Density Parity-Check (LDPC) codes on the Binary Symmetric Channel. In the PPBF, the flipping operation is performed in a probabilistic manner which is shown to improve significantly the error correction performance. The advantage of the PPBF also comes from the fact that no global computation is required during the decoding process and that all the computations can be executed in the local computing units and in-parallel. The PPBF provides a considerable improvement of the operating frequency and complexity, compared to other known BF decoders, while obtaining a significant gain in error correction. An improved version of the PPBF, called non-syndrome PPBF (NS-PPBF) is also introduced, in which the global syndrome check is moved out of the critical path and a new terminating mechanism is proposed. In order to show the superiority of the new decoders in terms of hardware efficiency and decoding throughput, the corresponding hardware architectures are presented in the second part of the paper. The ASIC synthesis results confirm that the operating frequency of the proposed decoders is significantly improved, compared to that of the BF decoders in the literature while requiring lower complexity to be efficiently implemented.

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Section: Introductionmentioning

confidence: 85%

Section: Introductionmentioning

confidence: 99%

A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes

Ghaffari

Kessal

et al. 2019

IEEE Trans. Circuits Syst. I

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“…Therefore, we randomly disturb the state of each VNU to be able to escape from the trapping set. Of course, one may question that such disturbance could adversely affect the normal behavior of the VNU, but theoretical results indicate that this side effect does not significantly increase the number of iterations [11]. If the GaB decoder does not converge within user-defined number of (k) iterations, then we apply this probabilistic strategy (Probabilistic GaB) to escape from trapping set.…”

Section: Probabilistic Gab Algorithmmentioning

confidence: 99%

“…Moreover, the probability function can be applied to the decoder in various positions. For example, in PGDBF decoder [11] the probabilistic function is applied during the final output decision of a VNU for deciding between flipping the channel value or not. In Stochastic GaB [12], the randomness effect acts on both messages exchanged mutually between VNU and CNU.…”

Section: Probabilistic Gab Algorithmmentioning

confidence: 99%

Analysis and implementation of resource efficient probabilistic Gallager B LDPC decoder

Unal

Ghaffari

Akoglu

et al. 2017

2017 15th IEEE International New Circuits and Systems Conference (NEWCAS)

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Low-Density-Parity-Check (LDPC) codes have gained popularity in communication systems and standards due to their capacity-approaching error-correction performance. In this paper, we first expose the tradeoff between decoding performance and hardware performance across three LDPC hard-decision decoding algorithms: Gallager B (GaB), Gradient Descent Bit Flipping (GDBF), and Probabilistic Gradient Descent Bit Flipping (PGDBF). We show that GaB architecture delivers the best throughput while using fewest Field Programmable Gate Array (FPGA) resources, however performs the worst in terms of decoding performance. We then modify the GaB architecture, introduce a new Probabilistic stimulation function (PGaB), and achieve dramatic decoding performance improvement over the GaB, exceeding the performance of GDBF, without sacrificing its superior maximum operating frequency.

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“…In this paper, this is called the improved MWSF (IMWSF) algorithm. Since then, there have been proposals of an average probability and stopping criterion weighted symbol flipping (APSCWSF) algorithm [18,19], multiple-vote symbol flipping (MV-SF) algorithm [20,21,22] and so on [23,24]. …”

Section: Introductionmentioning

confidence: 99%

Sum of the Magnitude for Hard Decision Decoding Algorithm Based on Loop Update Detection

Meng

Zhao

Tian

et al. 2018

Sensors

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In order to improve the performance of non-binary low-density parity check codes (LDPC) hard decision decoding algorithm and to reduce the complexity of decoding, a sum of the magnitude for hard decision decoding algorithm based on loop update detection is proposed. This will also ensure the reliability, stability and high transmission rate of 5G mobile communication. The algorithm is based on the hard decision decoding algorithm (HDA) and uses the soft information from the channel to calculate the reliability, while the sum of the variable nodes’ (VN) magnitude is excluded for computing the reliability of the parity checks. At the same time, the reliability information of the variable node is considered and the loop update detection algorithm is introduced. The bit corresponding to the error code word is flipped multiple times, before this is searched in the order of most likely error probability to finally find the correct code word. Simulation results show that the performance of one of the improved schemes is better than the weighted symbol flipping (WSF) algorithm under different hexadecimal numbers by about 2.2 dB and 2.35 dB at the bit error rate (BER) of 10−5 over an additive white Gaussian noise (AWGN) channel, respectively. Furthermore, the average number of decoding iterations is significantly reduced.

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Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping

Cited by 28 publications

References 17 publications

A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes

A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes

Analysis and implementation of resource efficient probabilistic Gallager B LDPC decoder

Sum of the Magnitude for Hard Decision Decoding Algorithm Based on Loop Update Detection

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