Efficient Hardware Verification Using Machine Learning Approach

Survey on Machine Learning Algorithms Enhancing the Functional Verification Process

“…Critical modelling parameters such as hidden layers count, number of neurons per layer and activation function per layer are not presented by the authors. Authors in [13] used four-layered and six-layered DNN models on a simple three-level circuit: OR → Adder → Multiplexer. Training and testing were carried out on the Keras platform using JetBrains PyCharm IDE.…”

“…Approaches, evaluation processes, and results are the metrics on which the comparison is based on. Although the selected research contributions [13,14,20], differ in conditions on which work is conducted, Table 6 provide a means of contrasting and comparing different contributions. nodes are organized and connected is defined by network topology.…”

“…Other attempts incorporated additional different ML models such as Markov models and inductive logic programming to reach a faster coverage convergence rate [6][7][8]. More recent research in the domain of stimulus and test generation used a combination of supervised and unsupervised ML models such as neural networks, random forest and support vector machines to reduce the amount of needed input iterations and testcases to reach the planned coverage goals [9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28]. In the scope of coverage collection, there are studies that show improvements in both the runtime of simulations that capture coverage and the percentage of coverage reached, when either a supervised or unsupervised ML model is used [29][30][31].…”

“…ReLU is chosen as the activation function. The contribution in [13] uses DNN with a count of two hidden layers in one experiment and a count of four in another trial. The selected activation function was ReLU and it was the choice for the two trails conducted.…”

“…Testing NN model performance on a case study implementing an RISC processor is of great interest as the results will indicate the performance of the novel approach in block-level testing other than system on chips SoCs. The study in [13] took the opposite approach in selecting the DUT to conduct the study. Authors used simple logic gates in their simulation iterations.…”