Efficient implementation of a fractal color image compression on FPGA

Son, Thai Nam; Long, Tran Van; Thang, Hoang Manh; Dzung, Nguyen Tien

doi:10.1109/socpar.2013.7054124

Cited by 3 publications

(3 citation statements)

References 7 publications

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Section: Introductionmentioning

confidence: 99%

“…To the best of our knowledge, there is no certain hardware work developed for encoding colour images except that proposed in [34]. According to [34], a soft-core processor designed for Xilinx FPGA has been used for coding a colour image. In the process, the RGB components of the colour image are transformed into YUV components, and then fractal coding is performed in different sampling modes of 4:4:4, 4:2:2, 4:2:0, 4:1:1 for attaining a higher compression rate.…”

Section: Introductionmentioning

confidence: 99%

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Deep Pipeline Architecture for Fast Fractal Color Image Compression Utilizing Inter-Color Correlation

et al. 2022

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Fractal compression technique is a well-known technique that encodes an image by mapping the image into itself and this requires performing a massive and repetitive search. Thus, the encoding time is too long, which is the main problem of the fractal algorithm. To reduce the encoding time, several hardware implementations have been developed. However, they are generally developed for grayscale images, and using them to encode colour images leads to doubling the encoding time 3x at least. Therefore, in this paper, new high-speed hardware architecture is proposed for encoding RGB images in a short time. Unlike the conventional approach of encoding the colour components similarly and individually as a grayscale image, the proposed method encodes two of the colour components by mapping them directly to the most correlation component with a searchless encoding scheme, while the third component is encoded with a search-based scheme. This results in reducing the encoding time and also in increasing the compression rate. The parallel and deep-pipelining approaches have been utilized to improve the processing time significantly. Furthermore, to reduce the memory access to the half, the image is partitioned in such a way that half of the matching operations utilize the same data fetched for processing the other half of the matching operations. Consequently, the proposed architecture can encode a 1024x1024 RGB image within a minimal time of 12.2 ms, and a compression ratio of 46.5. Accordingly, the proposed architecture is further superior to the state-of-the-art architectures.INDEX TERMS Digital circuits, field programmable gate arrays, fractal colour image compression, parallel architectures, pipeline processing.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Deep Pipeline Architecture for Fast Fractal Color Image Compression Utilizing Inter-Color Correlation

et al. 2022

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“…Around the transformations [11], extraction of characteristics [12] or any other type of massive matrix operation, object detection and recognition and route planning, Programmable Logic Devices (PLD) have been used, since they require low power and a small amount of space to work [13,14] in addition to having the ability to perform real-time implementations, working with static and moving images [15], which requires thousands of iterations per second, with maximum use of FPGA resources, both in the combinatorial part (LUT) as in its storage part (memory bank), making efficient the implementations made with this type of devices [16,17]. The acquisition of real-time images has become an everyday task, using conventional cameras and stereo cameras for capturing in 3D [18,19], in which applications with digital programmable devices have been made to perform high-speed processing, achieving solutions where a single FPGA is used that replaces systems of multiple architectures that required connections and conversions of information, slowing down actions on processes in jobs where short response times are required [20,21].…”

Section: Introductionmentioning

confidence: 99%

Transformation and dynamic visualization of images from computer through an FPGA in a matrix of LED

2019

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This article shows the implementation of a system that uses a graphic interface to load a digital image into a programmable logic device, which is stored in its internal RAM memory and is responsible for visualizing it in a matrix of RGB LEDs, so that This way, the LEDs show an equivalent to the image that was sent from the PC, conserving an aspect ratio and respecting as much as possible the color of the original image. To carry out this task, a Matlab script was designed to load the image, convert and format the data, which are transmitted to the FPGA using the RS232 protocol. The FPGA is in charge of receiving them, storing them and generating all the signals of control and synchronization of the system including the control of the PWM signals necessary to conserve the brightness of each one of the LEDs. This system allows the visualization of static images in standard formats and, in addition, thanks to the flexibility of the hardware used, it allows the visualization of moving images type GIF.

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