Efficient implementation of a real-time dynamic synthetic aperture beamformer

Park, Jong-Ho; Lee, Jongpil; Kim, Do-Hyung; Kim, Min‐Soo; Chang, Jin Ho; Song, Tai-Kyong; Yoo, Yangmo

doi:10.1109/ultsym.2012.0562

Cited by 4 publications

(4 citation statements)

References 5 publications

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“…A recursive and iterative method can be used to compute the square roots efficiently [49]. In [50] only every 32nd delay is truly computed and the remaining delays are interpolated. Some works and industrial products have focused on a low power, portable imager implementation [1]- [6], [51].…”

Section: Previous Workmentioning

confidence: 99%

Efficient Sample Delay Calculation for 2-D and 3-D Ultrasound Imaging

Ibrahim

Hager

Bartolini

et al. 2017

IEEE Trans. Biomed. Circuits Syst.

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Abstract-Ultrasound imaging is a reference medical diagnostic technique thanks to its blend of versatility, effectiveness and moderate cost. The core computation of all ultrasound imaging methods is based on simple formulae, except for those required to calculate delays with high precision and throughput. Unfortunately, advanced 3D systems require the calculation or storage of billions of such delay values per frame, which is a challenge. In 2D systems, this requirement can be four orders of magnitude lower, but efficient computation is still crucial in view of low-power implementations that can be battery-operated, enabling usage in rescue scenarios.In this paper we explore two smart designs of the delay generation function. To quantify their hardware cost, we implement them on FPGA and study their footprint and performance. We evaluate how these architectures scale to different ultrasound applications, from a low-power 2D system to a next-generation 3D machine. When using numerical approximations, we demonstrate the ability to generate delay values with sufficient throughput to support 10000-channel 3D imaging at up to 30 fps while using 63% of a Virtex 7 FPGA, requiring 24 MB of external memory accessed at about 32 GB/s bandwidth. Alternatively, with similar FPGA occupation, we show an exact calculation method that reaches 24 fps on 1225-channel 3D imaging and does not require external memory at all. Both designs can be scaled to use a negligible amount of resources for 2D imaging in low-power applications, and for ultrafast 2D imaging at hundreds of frames per second.

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Section: Previous Workmentioning

confidence: 99%

Efficient Sample Delay Calculation for 2-D and 3-D Ultrasound Imaging

Ibrahim

Hager

Bartolini

et al. 2017

IEEE Trans. Biomed. Circuits Syst.

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“…Other works [15], [16], [17], [18] have shown that a feasible alternative is to try to compute all delay coefficients onthe-fly on-chip. Since this computation involves the evaluation of complex functions like square roots, it is mandatory to identify accurate, fast and low-area approximation circuits [19], [20]. In particular, we have shown [5], [6] how a highly efficient architecture can be devised by accepting some inaccuracy in the calculation of the delays.…”

Section: Resultsmentioning

confidence: 99%

Apodization scheme for hardware-efficient beamformer

Ibrahim

Angiolini

Arditi

et al. 2016

2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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Abstract-3D ultrasound is an emerging diagnostic technique that extends standard ultrasound imaging by capturing volumes, instead of planes. This brings completely new diagnostic opportunities, among which the possibility of disjoining image acquisition and analysis, thus enabling remote diagnosis, which would bring obvious medical and economic benefits.Unfortunately, 3D ultrasound is several orders of magnitude more computationally complex than 2D imaging. Therefore, algorithmic improvements to simplify the processing are mandatory in order to conceive cheap, portable, low-power imagers.The kernel of the 3D imaging process, called beamforming, consists essentially of computing delay and apodization profiles. We have previously devised an approximation of the delay calculation stage, which dramatically reduces hardware complexity. Unfortunately, this approximation introduces an intrinsic degree of inaccuracy that can be characterized as added image noise.In this paper, we identify an efficient approximated approach to the calculation of apodization profiles, that additionally minimizes (-76%) the error introduced during delay calculation. Together, these two techniques enable an efficient computation of 3D ultrasound images.

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“…Compared with the quad Virtex-5 LX330 FPGA solution [33] our integrated approach provides only 2.75× less processing throughput at a much smaller form factor and power budget. The 8-core TI Keystone DSP-based solution [36] targets low-power, low-cost ultrasound devices.…”

Section: B Estimated Powermentioning

confidence: 99%

“…Since Ekho can be scaled down to support such setups, a comparison with these 2-D systems is appropriate. In [33], a 128 channel synthetic aperture 2-D BF built from four Virtex-5 LX330 FPGAs is presented. Sixteen SLs are computed in parallel at a sampling rate of 40 MHz.…”

Section: Introductionmentioning

confidence: 99%

Ekho: A 30.3W, 10k-Channel Fully Digital Integrated 3-D Beamformer for Medical Ultrasound Imaging Achieving 298M Focal Points per Second

Hager

Bartolini

Benini

2016

IEEE Trans. VLSI Syst.

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3-D medical ultrasound imaging enables new diagnostic possibilities and modalities. In a computational process called beamforming, a 3-D volume is reconstructed from several thousands of analog signals. Today's systems rely on massive analog preprocessing to reduce the computational burden of the subsequent digital processing system. In this paper, we present a configurable beamformer (BF) architecture, which demonstrates for the first time that it is possible to implement the entire 3-D delay and sum beamforming fully digitally and on one single chip, without requiring the off-chip memories. We present a presilicon implementation of a single-chip BF in an advanced 28-nm silicon-on-insulator technology. The BF targets a fully sampled 10k element 8-MHz bandwidth transducer head and is able to produce 298.1 M focal points (FPs) per secondenough to produce a high-resolution volume with 16.3 MFP at 15 Hz. All delays are computed online and on-chip to eliminate the power-hungry external memories for delay storage. The final design (register-transfer-level and floorplan) has a complexity of 342 M gate equivalents requiring 1.68 cm 2 of area. The core power is estimated to be 30.3 W, resulting in an unprecedented power efficiency of 98.4 G beamforming operations per watt.Index Terms-28-nm silicon-on-insulator (SOI), 3-D ultrasound, delay index computation, medical imaging, single-chip beamforming.

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Efficient implementation of a real-time dynamic synthetic aperture beamformer

Cited by 4 publications

References 5 publications

Efficient Sample Delay Calculation for 2-D and 3-D Ultrasound Imaging

Efficient Sample Delay Calculation for 2-D and 3-D Ultrasound Imaging

Apodization scheme for hardware-efficient beamformer

Ekho: A 30.3W, 10k-Channel Fully Digital Integrated 3-D Beamformer for Medical Ultrasound Imaging Achieving 298M Focal Points per Second

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