Efficient Implementation of a Symbol Timing Estimator for Broadband PLC

Abstract

Broadband Power Line Communications (PLC) have taken advantage of the research advances in multi-carrier modulations to mitigate frequency selective fading, and their adoption opens up a myriad of applications in the field of sensory and automation systems, multimedia connectivity or smart spaces. Nonetheless, the use of these multi-carrier modulations, such as Wavelet-OFDM, requires a highly accurate symbol timing estimation for reliably recovering of transmitted data. Furthermore, the PLC channel presents some particularities that prevent the direct use of previous synchronization algorithms proposed in wireless communication systems. Therefore more research effort should be involved in the design and implementation of novel and robust synchronization algorithms for PLC, thus enabling real-time synchronization. This paper proposes a symbol timing estimator for broadband PLC based on cross-correlation with multilevel complementary sequences or Zadoff-Chu sequences and its efficient implementation in a FPGA; the obtained results show a 90% of success rate in symbol timing estimation for a certain PLC channel model and a reduced resource consumption for its implementation in a Xilinx Kyntex FPGA.

Embedded Implementation of VHR Satellite Image Segmentation

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“…Este proceso se realiza para varios desplazamientos, y se elige como criterio de ajuste fino al desplazamiento para el que se obtenga el menor MSE respecto a la ACS esperada idealmente. Luego, en [Nombela 2015a] los autores proponen la implementación de la etapa de sincronización gruesa del anterior algoritmo, e incluyen secuencias ZC como símbolo piloto, además de CSS multinivel. El canal PLC de banda ancha suele considerarse cuasi estático, es decir, constante para toda la duración de la trama, por lo que suelen utilizarse símbolos piloto para la estimación de canal.…”