Efficient implementation of bit‐parallel fault tolerant polynomial basis multiplication and squaring over GF(2
            <i>
              <sup>m</sup>
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            )

Rashidi, Bahram; Sayedi, Sayed Masoud; Farashahi, Reza Rezaeian

doi:10.1049/iet-cdt.2015.0020

Cited by 10 publications

(10 citation statements)

References 21 publications

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“…The multiplication by field elements (x, x 2 , and x 3 ) are computed based on [54]. The hardware structures of multiplication by (x, x 2 , and x 3 ) are shown in Fig.…”

Section: Proposed Hardware Structure Of the Led Ciphermentioning

confidence: 99%

“…Asseen from the figure, this block is implemented based on bit‐wise XOR operations(addition in finite field

F_{2^{4}}

) and the multiplication by field elements( x ,

x^{2}

, and

x^{3}

) modulo irreducible polynomial

x^{4} + x + 1

. The multiplication by field elements( x ,

x^{2}

, and

x^{3}

) are computed based on [54]. The hardware structures ofmultiplication by ( x ,

x^{2}

, and

x^{3}

) are shown in Fig.…”

Section: Proposed Hardware Structures Of the Present Simon And Led mentioning

confidence: 99%

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Flexible structures of lightweight block ciphers PRESENT, SIMON and LED

Rashidi¹

2020

IET Circuits, Devices & Systems

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Security and privacy of the Internet of Things (IoT) systems are critical challenges in many data-sensitive applications. The IoT systems are constrained in terms of execution time, flexibility and computational resources. In recent years, many encryption algorithms have been proposed to provide the security of IoT communication. In this study, flexible and high-throughput hardware structures of the PRESENT, SIMON, and LED lightweight block ciphers are presented for IoT applications. The proposed flexible structures can perform various configurations of these block ciphers to support variable key sizes. For example, the PRESENT, SIMON, and LED ciphers support key sizes (80, 128 bits), (96, 144, 128, 192, and 256 bits), and (64, 128 bits), respectively. Therefore, these architectures provide versatile implementations that enable adaptive security level using a variable key size. In the proposed structures, sub-blocks of the ciphers are implemented based on optimised circuits. In the PRESENT and LED ciphers, the S-boxes are implemented based on area-optimised logic circuits. The implementation results of proposed flexible architectures are achieved in 180 nm CMOS technology. Area, throughput and throughput/area of the proposed structures have improved compared to other related works.

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“…The multiplication by field elements (x, x 2 , and x 3 ) are computed based on [54]. The hardware structures of multiplication by (x, x 2 , and x 3 ) are shown in Fig.…”

Section: Proposed Hardware Structure Of the Led Ciphermentioning

confidence: 99%

“…Asseen from the figure, this block is implemented based on bit‐wise XOR operations(addition in finite field

F_{2^{4}}

) and the multiplication by field elements( x ,

x^{2}

, and

x^{3}

) modulo irreducible polynomial

x^{4} + x + 1

. The multiplication by field elements( x ,

x^{2}

, and

x^{3}

) are computed based on [54]. The hardware structures ofmultiplication by ( x ,

x^{2}

, and

x^{3}

) are shown in Fig.…”

Section: Proposed Hardware Structures Of the Present Simon And Led mentioning

confidence: 99%

Flexible structures of lightweight block ciphers PRESENT, SIMON and LED

Rashidi¹

2020

IET Circuits, Devices & Systems

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“…If A, B ∈ F 2 16 for implementation multiplication by (0×0002) −1 (or z −1 ), i.e. B = z −1 A mod f 3 (z) we have [20,21] B = [a 0 , (a 15 ⊕ a 0 ), a 14 , (a 13 ⊕ a 0 ), a 12 , (a 11 ⊕ a 0 ), a 10 , a 9 , a 8 , a 7 , a 6 , (a 5 ⊕ a 0 ), (a 4 ⊕ a 0 ), a 3 , a 2 , a 1 ] .…”

Section: Hardware Structure Of the S-box Smentioning

confidence: 99%

“…The sub‐blocks multiplication, inversion and squaring are defined over

F_{2^{4}}

with primitive polynomial

f_{2} false(z false) = z^{4} + z + 1

. The multiplication and inversion, squaring operations over

F_{2^{4}}

are implemented based on [19, 20]. However, in the proposed implementation, we applied further optimisation in the structures of multiplication and inversion over

F_{2^{4}}

for reducing CPD and area consumption.…”

Section: Proposed Hardware Structures For 128 192 and 256 Bit Keysmentioning

confidence: 99%

“…If

bold-italicA, bold-italicB \in F_{2^{16}}

for implementation multiplication by (0×0002) −1 (or

z^{- 1}

), i.e.

bold-italicB = z^{- 1} bold-italicA \mod f_{3} false(z false)

we have [20, 21]

\begin{matrix} right leftthickmathspace.5em \\ B = & [a_{0}, (a_{15} \oplus a_{0}), a_{14}, (a_{13} \oplus a_{0}), a_{12}, (a_{11} \oplus a_{0}), \\ a_{10}, a_{9}, a_{8}, a_{7}, a_{6}, (a_{5} \oplus a_{0}), (a_{4} \oplus a_{0}), a_{3}, a_{2}, a_{1}] . \end{matrix}

As seen from Fig. 11 b , the multiplication by

false(0 \times 0002 {false)}^{- 1}

is implemented based on five XOR gates.…”

Section: Proposed Hardware Structures For 128 192 and 256 Bit Keysmentioning

confidence: 99%

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Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher

Rashidi¹

2020

IET Computers & Digital Techniques

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In this study, high-throughput and flexible hardware implementations of the CLEFIA lightweight block cipher are presented. A unified processing element is designed and shared for implementing of generalised Feistel network that computes round keys and encryption process in the two separate times. The most complex blocks in the CLEFIA algorithm are substitution boxes (S 0 and S 1). The S 0 S-box is implemented based on area-optimised combinational logic circuits. In the proposed S-box structure, the number of logic gates and critical path delay are reduced by using the simplification of computation terms. The S-box S 1 consists of three steps: a field inversion over F 2 8 and two affine transformations over F 2. The inversion operation is implemented over the composite field F (2 4) 2 instead of inversion over F 2 8 which is an important factor for the reduction of area consumption. In addition, we proposed a flexible structure that can perform various configurations of CLEFIA to support variable key sizes: 128, 192 and 256 bit. Implementation results of the proposed architectures in 180 nm complementary metal-oxide-semiconductor technology for different key sizes are achieved. The results show improvements in terms of execution time, throughput and throughput/area compared with other related works.

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Error‐correcting cryptographic S‐boxes with multiple error detection and correction

Rashidi.

2023

Circuit Theory & Apps

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SummaryIn this paper, the error‐correcting 4‐bit S‐boxes for cryptography applications with multiple error detection and correction are presented. Three 4‐bit S‐boxes which are used in the lightweight block ciphers PRESENT, Midori, and KLEIN are considered for implementation of the error‐correcting method. The proposed method does not require two redundant S‐boxes for repairing the S‐box. The main circuit of the S‐box is implemented concurrently with the low‐cost error‐correcting part of the structure. This reduces the overall area consumption and delay of the proposed error‐correcting method (the area consists of the 4‐bit S‐box and self‐checking/error‐correcting circuits). In the proposed error‐correcting method, the outputs of the S‐box are tested individually and it can detect and repair transient and permanent faults simultaneously. Therefore, the structure can detect and repair the single, double, triple, and quadruple faults at a time. The area and timing results, in 180 nm CMOS technology, show the proposed structures are acceptable in terms of area and delay overheads than those of the other methods.

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Efficient implementation of bit‐parallel fault tolerant polynomial basis multiplication and squaring over GF(2 ^m )

Cited by 10 publications

References 21 publications

Flexible structures of lightweight block ciphers PRESENT, SIMON and LED

Flexible structures of lightweight block ciphers PRESENT, SIMON and LED

Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher

Error‐correcting cryptographic S‐boxes with multiple error detection and correction

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Efficient implementation of bit‐parallel fault tolerant polynomial basis multiplication and squaring over GF(2 m )

Cited by 10 publications

References 21 publications

Flexible structures of lightweight block ciphers PRESENT, SIMON and LED

Flexible structures of lightweight block ciphers PRESENT, SIMON and LED

Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher

Error‐correcting cryptographic S‐boxes with multiple error detection and correction

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Product

Resources

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Efficient implementation of bit‐parallel fault tolerant polynomial basis multiplication and squaring over GF(2 ^m )