“…A particular attention was devoted to this difficulty (see [9], [lo]). In order to keep as much as possible the improvement brought by the reduction of the arithmetic complexity of these composite algorithms without exceeding too many resources available on DSP's, we suggest an optimal data memory organization based on the proposed one given in1 [9], [lo]. The basic idea, as shown in [9], consists in defining one delay line for ordering data and one array for storing fixed FIR sub-fiiters coefficients in such a way that 6(N + 1)I1.,, m, pointers registers are simplified to only two.…”