Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS

Heyse, Karel; Davidson, Tom; Vansteenkiste, Elias; Bruneel, Karel; Stroobandt, Dirk

doi:10.1109/fpl.2013.6645516

Cited by 20 publications

(17 citation statements)

References 13 publications

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“…In the previous work on parameterized VCGRA implementations, authors of [2] parameterized the LUTs and interconnects of the VCGRA. They were able to save 50% of the LUT resources.…”

Section: Fully Parameterized Vcgramentioning

confidence: 99%

“…In order to overcome this limitation for the FPGAs, VCGRAs are proposed [2]. The programming model for the VCGRAs is different by the fact that the code can be written on a higher abstraction level.…”

Section: Introductionmentioning

confidence: 99%

“…Authors in [2] have shown that conventional VCGRA implementations use LUTs of the FPGA to realize reconfigurable virtual switch blocks, virtual registers and other virtual components. With the help of parameterized configuration, the authors were able to map the virtual components to the lower level physical resources (settings registers were mapped onto configuration memory and VSBs were mapped onto switch blocks) of an FPGA.…”

Section: Introductionmentioning

confidence: 99%

“…This saves a significant amount of functional resources (LUTs) of an FPGA. However, the work in [2] was limited to parameterize the LUTs of the PEs and inter-connect (VSBs) of the VCGRA only, thus resulting in a semi-parameterized VCGRA. In this paper, our main contribution is to parameterize not only the PEs and VSBs, but also the connections within each PE (intra-connect) using Tunable Connections (TCONs) [4].…”

Section: Introductionmentioning

confidence: 99%

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A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

Kulkarni

Vasteenkiste

Stroobandt

et al. 2016

2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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Abstract-Field Programmable Gate Arrays (FPGAs) have proven their potential in accelerating High Performance Computing (HPC) Applications. Conventionally such accelerators predominantly use, FPGAs that contain fine-grained elements such as LookUp Tables (LUTs), Switch Blocks (SB) and Connection Blocks (CB) as basic programmable logic blocks. However, the conventional implementation suffers from high reconfiguration and development costs. In order to solve this problem, programmable logic components are defined at a virtual higher abstraction level. These components are called Processing Elements (PEs) and the group of PEs along with the inter-connection network form an architecture called a Virtual Coarse-Grained Reconfigurable Array (VCGRA). The abstraction helps to reconfigure the PEs faster at the intermediate level than at the lower-level of an FPGA.Conventional VCGRA implementations (built on top of the lower levels of the FPGA) use functional resources such as LUTs to establish required connections (intra-connect) within a PE. In this paper, we propose to use the parameterized reconfiguration technique to implement the intra-connections of each PE with the aim to reduce the FPGA resource utilization (LUTs). The technique is used to parameterize the intra-connections with parameters that only change their value infrequently (whenever a new VCGRA function has to be reconfigured) and that are implemented as constants. Since the design is optimized for these constants at every moment in time, this reduces the resource utilization. Further, interconnections (network between the multiple PEs) of the VCGRA grid can also be parameterized so that both the inter-and intraconnect network of the VCGRA grid can be mapped onto the physical switch blocks of the FPGA. For every change in parameter values a specialized bitstream is generated on the fly and the FPGA is reconfigured using the parameterized run-time reconfiguration technique. Our results show a drastic reduction in FPGA LUT resource utilization in the PE by at least 30% and in the intra-network of the PE by 31% when implementing an HPC application.

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“…In the previous work on parameterized VCGRA implementations, authors of [2] parameterized the LUTs and interconnects of the VCGRA. They were able to save 50% of the LUT resources.…”

Section: Fully Parameterized Vcgramentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

Kulkarni

Vasteenkiste

Stroobandt

et al. 2016

2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

Self Cite

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show abstract

“…The PPC contains bitstreams expressed in the form of Boolean functions of infrequently changing parameters. In [5] it is explained how a parameterized design is mapped on to the virtual Look Up Tables called Tunable Look Up Tables (TLUTs). TLUTs are intermediate representations of conventional FPGA physical LUTs that contain truth table entries expressed as Boolean functions of the parameters.…”

Section: State Of the Artmentioning

confidence: 99%

Power measurements and analysis for dynamic circuit specialization

Kulkarni

Bonamy²,

Stroobandt

2015

2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

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Abstract-Dynamic Circuit Specialization (DCS) is a technique for optimized FPGA implementation and is built on top of Partial Reconfiguration (PR). Dynamic Partial Reconfiguration (DPR) provides an opportunity to share the silicon area between different Partially Reconfigurable Modules (PRMs) and therefore results in smaller and faster designs that potentially also reduce the power consumption. In this paper, we show that energy consumption is an important factor that has to be considered while implementing a parameterized design using DCS. In order to make a good choice for implementing a parameterized design with the goal of power optimized implementation, it is important to have a good power consumption estimate of the Dynamic Circuit Specialization. In this context, our paper presents a detailed investigation of the power consumption of a parameterized design implemented using DCS on the Xilinx Zynq-SoC FPGA. We propose an energy analysis of DCS and investigate the benefits of the use of DCS in comparison with a classic static FPGA implementation. We see that the power needed for the reconfiguration is much higher than the gain in power using the reconfiguration over the static implementation. An important reason is because of the CPU involved during the reconfiguration and the interface between the AXI bus and the HWICAP. To reduce the reconfiguration power, we include a clock gating technique to the reconfiguration interface AXI-HWICAP that makes DCS more power efficient. We also relate the power gain to the size of the implementation and to the allowed time to reconfigure versus the useful run time. We conclude that for an implementation with 10 FIR filters, the reconfiguration time should not take more than 30.3% of the total time in order to remain energy efficient. Considering a specific use case with 10 FIR filters at a reconfiguration rate of 0.01, the energy consumption using DCS implementation is 20.5% lower than using the static FIR.

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Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms

Werner

Fricke

Shahin

et al. 2019

Lecture Notes in Computer Science

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Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS

Cited by 20 publications

References 13 publications

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

Power measurements and analysis for dynamic circuit specialization

Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms

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