2012
DOI: 10.1049/iet-cds.2011.0283
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Efficient inclusive analytical model for delay estimation of multi-walled carbon nanotube interconnects

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Cited by 12 publications
(4 citation statements)
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“…In this section, the different parameters of an MWCNT interconnect is estimated and compared with the traditional Cu interconnect. All interconnect parameters used are obtained from ITRS 2005 [18], as summarized in table I. In this paper, the diameter of MWCNT and Cu wire is set equal to minimum width of interconnects at each technology node.…”
Section: Comparative Analysis Of Interconnectsmentioning
confidence: 99%
“…In this section, the different parameters of an MWCNT interconnect is estimated and compared with the traditional Cu interconnect. All interconnect parameters used are obtained from ITRS 2005 [18], as summarized in table I. In this paper, the diameter of MWCNT and Cu wire is set equal to minimum width of interconnects at each technology node.…”
Section: Comparative Analysis Of Interconnectsmentioning
confidence: 99%
“…In the last few decades, carbon nanotubes (CNTs) have attracted a lot of attention as next-generation interconnect technology [6], [7]. CNTs exhibit higher ampacity (maximum current-carrying capacity), larger thermal conductivity, and long mean free path due to their strong C-C bonding in comparison with copper (Cu) counterpart [8]- [10].…”
Section: Introductionmentioning
confidence: 99%
“…However, conventional materials such as aluminium (Al) and copper (Cu) confront to maintain the performance and functionality of current demand. Although an increase in resistivity primarily responsible for higher resistance of metallic interconnect and becomes encumbrance due to hillock formation, surface, and grain boundary scattering [1]. Besides, the crosstalk‐induced delay becomes the bottleneck for advanced technology due to the closer proximity of wires and higher interconnect density [2].…”
Section: Introductionmentioning
confidence: 99%
“…parasitic values increases that cause the degradation of interconnect performance and leads to higher propagation delay and more power dissipation. The rise in power dissipation also causes an increase in joule heating that results in electromigration induced hillock and void formation [1]. These limitations of Cu interconnect is technology dependent and are going to be more severe for the future generation of VLSI chips.…”
Section: Introductionmentioning
confidence: 99%