Efficient Integer DCT Architectures for HEVC

Meher, Pramod Kumar; Park, Soo‐Jin; Mohanty, Basant Kumar; Lim, Khoon Seong; Yeo, Chuohao

doi:10.1109/tcsvt.2013.2276862

Cited by 175 publications

(140 citation statements)

References 15 publications

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“…그리고 2013년에 Zhu는 파 이프라인 역변환 구조를 제안했다 [6] . 게다가 근사 DCT 알 고리즘 기반으로 Pramod는 2013년 효율적인 상수 행렬 곱셈 방식을 사용함으로써 병렬 1-D 정수형 DCT 구조를 제안했다 [7] . 본 논문에서는 VP9 디코더 내의 행렬 기반 정수형 역변 환 방식의 하드웨어 구조를 제안한다.…”

Section: 일정한 영상을 제공한다unclassified

Integer Inverse Transform Structure Based on Matrix for VP9 Decoder

Lee¹,

Hwang²,

Kim³

et al. 2016

Journal of the Institute of Electronics and Information Enginee

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In this paper, we propose an efficient integer inverse transform structure for vp9 decoder. The proposed structure is a hardware structure which is easy to control and requires less hardware resources, and shares algorithms for realizing entire DCT(Discrete Cosine Transform), ADST(Asymmetric Discrete Sine Transform) and WHT(Walsh-Hadamard Transform) in vp9. The integer inverse transform for vp9 google model has a fast structure, named butterfly structure. The integer inverse transform for google C model, unlike universal fast structure, takes a constant rounding shift operator on each stage and includes an asymmetrical sine transform structure. Thus, the proposed structure approximates matrix coefficient values for all transform mode and is used to matrix operation method. With the proposed structure, shared operations for all inverse transform algorithm modes can be possible with reduced number of multipliers compared to the butterfly structure, which in turn manages the hardware resources more efficiently.

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Section: 일정한 영상을 제공한다unclassified

Integer Inverse Transform Structure Based on Matrix for VP9 Decoder

Lee¹,

Hwang²,

Kim³

et al. 2016

Journal of the Institute of Electronics and Information Enginee

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“…Thus, many attempts had been made to shorten the adder-delay of the DCT SFG's critical path. One of the most effective approaches is an approximation DCT method, such as the approximation model by M. Parfieniuk et al [10] and Integer DCT (IntDCT) by P. K. Meher et al [9].…”

Section: Introductionmentioning

confidence: 99%

Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC

Hoang

Pham

2018

IEICE Electron. Express

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In this paper, the minimum adder-delay Discrete Cosine Transform (DCT) architecture is proposed using the Adaptive CORDIC (ACor) algorithm with fixed-rotation implementations. The proposed method has six different versions differ from the number of DCT point, i.e., 8-point (8p), 16-point (16p), and 32-point (32p), and the number of ACor stages, i.e., 2-Stage (2S) and 3-Stage (3S). The Altera Stratix IV and Stratix II FPGAs were used to built and verified the implementations. The 2S designs of 8p, 16p, and 32p DCT achieved the timing performances of four, five, and six adder-delay results, respectively. The proposed method was proven to have the best timing performances, good accuracy results, and adequate resources cost in comparison with other recent works.

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“…The hardware cost of transpose buffer will continue to increase in next-generation video coding standard, since it will include 64×64 and 128×128 DCT/IDCT operations [12]. Therefore, it is necessary to investigate efficient circuit architectures to reduce hardware implementation cost and computational complexity [13][14][15].…”

Section: Introductionmentioning

confidence: 99%