Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network

Raut, Gopal; Bhartiy, Vishal; Rajput, Gunjan; Khan, Sajid; Beohar, Ankur; Vishvakarma, Santosh Kumar

doi:10.1007/978-981-32-9767-8_28

Cited by 5 publications

(2 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We analyze and discuss the impact of technology scaling on circuit's physical parameters like area, power and delay. Experimental evaluations show that RECON as a MAC unit, has a lower area and power footprint as compared to the contemporary state-of-the-art designs proposed in [20]- [23]. Moreover, our proposed design architecture can support both signed and unsigned number representations.…”

Section: B Contributionsmentioning

confidence: 94%

RECON: Resource-Efficient CORDIC-Based Neuron Architecture

Raut

Rai

Vishvakarma

et al. 2021

IEEE Open J. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

Contemporary hardware implementations of artificial neural networks face the burden of excess area requirement due to resource-intensive elements such as multiplier and non-linear activation functions. The present work addresses this challenge by proposing a resource-efficient Coordinate Rotation Digital Computer (CORDIC)-based neuron architecture (RECON) which can be configured to compute both multiply-accumulate (MAC) and non-linear activation function (AF) operations. The CORDIC-based architecture uses linear and trigonometric relationships to realize MAC and AF operations respectively. The proposed design is synthesized and verified at 45nm technology using Cadence Virtuoso for all physical parameters. Implementation of the signed fixed-point 8-bit MAC using our design, shows 60% less area, latency, and power product (ALP) and shows improvement by 38% in area, 27% in power dissipation, and 15% in latency with respect to the state-of-the-art MAC design. Further, Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that worst-case mean is 189.73μW which is 63% of the state-of-the-art. INDEX TERMS AF, CORDIC, configurable architecture, MAC, neural network.

show abstract

Section: B Contributionsmentioning

confidence: 94%

RECON: Resource-Efficient CORDIC-Based Neuron Architecture

Raut

Rai

Vishvakarma

et al. 2021

IEEE Open J. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…DSP applications may be subject to the proposed MSR CORDIC. By regulating the internal dynamic range, the MSR CORDIC algorithm enhances signal to quantization of noise (SQNR) [12]. SQNR performs statistical properties both first and second order.…”

Section: ░ 2 Related Workmentioning

confidence: 99%

CORDIC Processors: A Comparative Perspective of Radix-8, Radix-4, and Radix-2

Rajesh

Parvateesam

Satyanarayana

et al. 2022

IJEER

View full text Add to dashboard Cite

Some data streaming applications make use of digital signal processing (DSP). The DSP algorithms include transcendental functions like trigonometry, inverse trigonometry, logarithms, exponentials, and other functions in addition to the basic arithmetic operations of multiplication and division. By modifying a few simple parameters, it is relatively simple to generate a large range of functions, including logarithmic, exponential, and trigonometric ones. Since the CPU needs around n rounds to process n bits of incoming data, the CORDIC radix-2 causes a substantial amount of latency. Therefore, radix-4 (which is radix-4 plus one) and radix-8 (which is radix-8 plus one) may be used to reduce the amount of time needed for the calculation. As a result, the total iterations drop from n/2 to n/4. As simulated and synthesized, it was shown that the radix-8 design had a significantly higher power consumption, with greater throughput than the radix-2 and radix-4 Coordinate Rotational Digital Computer (CORDIC) designs with an additional area overhead. The new algorithm also reduces the amount of twiddle elements to a minimum while also simplifying the address generating process. A novel approach makes integrating FFT processors on single chips much easier. This approach is demonstrated to be notably efficient in procedures such as SVD or matrix triangularization, in which the calculation of the rotation angle is necessary.

show abstract