Efficient management of custom instructions for run-time reconfigurable instruction set processors

Lam, Siew-Kei; Krishnan, B.N.; Srikanthan, Thambipillai

doi:10.1109/fpt.2006.270323

Cited by 5 publications

(4 citation statements)

References 9 publications

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“…We have described a design exploration methodology that computes a set of custom instructions from a given application in [6]. The custom instructions are represented by the intermediate format of the Trimaran compiler infrastructure [13].…”

Section: Proposed Techniquementioning

confidence: 99%

“…The custom instructions are represented by the intermediate format of the Trimaran compiler infrastructure [13]. In this paper, we extend the design exploration methodology in [6] to rapidly estimate the hardware area utilization for realizing custom instructions on a FPGA-based RFU. Figure 2(a) illustrates the target RFU model, which consists of a 2D array of programmable logic elements that are interconnected by the switches and routing bus.…”

Section: Proposed Techniquementioning

confidence: 99%

“…The proposed technique is an extension to the design exploration methodology that was presented in [6]. The methodology first identifies a set of custom instructions from the DFG (Data-Flow Graph) of an application.…”

Section: Introductionmentioning

confidence: 99%

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High level area estimation of custom instructions for FPGA-based reconfigurable processors

Lam

Srikanthan

2007

2007 6th International Conference on Information, Communications &Amp; Signal Processing

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Reconfigurable processors provide an attractive means to meet the constraints of embedded devices due to their instruction set extension capabilities. We propose a novel technique to estimate the area utilization of LUT (Look-Up Table) based FPGAs (Field Programmable Gate Arrays) for custom instruction realizations. The technique contributes to rapid design exploration by computing the hardware area utilization of custom instructions without actual hardware synthesis. The proposed area estimation technique is achieved in two stages. In the first stage, a set of partitions are obtained from the custom instruction data-paths based on some rule-sets that satisfy the FPGA constraints. Each partition represents a unique LUT configuration that can be implemented on a FPGA logic element. In the second stage, the partitions are combined to maximize the area efficiency on FPGA. We show that the proposed technique can overcome the limitation of existing datapath merging methods that are based on maximizing resource sharing. Experimental results show that an average of 12 unique LUT configurations (about 22% of the logic elements in the smallest Xilinx Virtex FPGA) can sufficiently cater to seven applications from the MiBench benchmark suite.

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Section: Proposed Techniquementioning

confidence: 99%

Section: Proposed Techniquementioning

confidence: 99%

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High level area estimation of custom instructions for FPGA-based reconfigurable processors

Lam

Srikanthan

2007

2007 6th International Conference on Information, Communications &Amp; Signal Processing

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“…The observations of the templates' characteristic (i.e. most of the frequently occurring templates are consumed by larger templates) were initially reported in our preliminary work in [LAM 2006a] for a restricted set of applications. In this paper, we performed proper template classification in order to study the statistical properties of the templates, and validated this characteristic with a larger set of applications.…”

Section: Introductionmentioning

confidence: 99%

Rapid evaluation of custom instruction selection approaches with FPGA estimation

Lam

Srikanthan

Clarke

2014

ACM Trans. Embed. Comput. Syst.

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________________________________________________________________________The main aim of this paper is to demonstrate that a fast and accurate FPGA estimation engine is indispensable in design flows for custom instruction (template) selection. The need for a FPGA estimation engine stems from the difficulty in predicting the FPGA performance measures of selected custom instructions. We will present a FPGA estimation technique that partitions the high-level representation of custom instructions into clusters based on the structural organization of the target FPGA, while taking into account general logic synthesis principles adopted by FPGA tools. In this work, we have evaluated a widely-used graph covering algorithm with various heuristics for custom instruction selection. In addition, we present an algorithm called Refined Largest Fit First (RLFF) that relies on a graph covering heuristic to select non-overlapping superset templates, which typically incorporate frequently used basic templates. The initial solution is further refined by considering overlapping templates that were ignored previously to see if their introduction could lead to higher performance. While RLFF provides the most efficient cover compared to the ILP method and other graph covering heuristics, FPGA estimation results reveals that RLFF leads to the worst performance in certain applications. It is therefore a worthy proposition to equip design flows with accurate FPGA estimation in order to rapidly determine the most profitable custom instruction approach for a given application.

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Accelerating identification of custom instructions for extensible processors

Deng

et al. 2011

IET Circuits Devices Syst.

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Efficient management of custom instructions for run-time reconfigurable instruction set processors

Cited by 5 publications

References 9 publications

High level area estimation of custom instructions for FPGA-based reconfigurable processors

High level area estimation of custom instructions for FPGA-based reconfigurable processors

Rapid evaluation of custom instruction selection approaches with FPGA estimation

Accelerating identification of custom instructions for extensible processors

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