Efficient modular testing of SoCs using dual-speed TAM architectures

Sehgal, A.; Chakrabarty, Krishnendu

doi:10.1109/date.2004.1268883

Cited by 13 publications

(10 citation statements)

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“…In addition, none of the above approaches accounts for the SOC hierarchy when designing TAMs. A limited number of research approaches have been presented to address the above issues separately in [33] and [35] (for multifrequency TAM design) and in [2], [3], [6], [14], [26], and [34] (for hierarchical SOC testing). Prior to outlining our contributions, we will summarize the relevance and limitations of these methods.…”

Section: B Motivation and Summary Of Contributionsmentioning

confidence: 99%

“…Later in [33], the ATE channels with high data rates are used to directly drive SOC TAM wires, and the heuristic approach based on rectangle packing from [18] was extended to optimize the dual-speed TAM architecture. In order to fully exploit the capability of state-of-the-art ATEs to drive different channels at different data rates, [33] and [35] were proposed. Most of the ATEs currently in use, however, do not have this feature and therefore cannot employ the proposed techniques.…”

Section: B Motivation and Summary Of Contributionsmentioning

confidence: 99%

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Multifrequency TAM design for hierarchical SOCs

Nicolici²

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The emergence of megacores in hierarchical systemon-a-chip (SOC) presents new challenges to electronic test automation. This paper describes a new framework for designing test access mechanisms (TAMs) for modular testing of hierarchical SOCs. We first explore the concept that TAMs on the same level of design hierarchy employ multiple frequencies for test data transportation. Then we extend this concept to hierarchical SOCs and, by introducing frequency converters at the inputs and outputs of the megacores, the proposed solution not only removes the constraint that the system level TAM width must be wider than the internal TAM width of the megacores, but also facilitates rapid exploration of the tradeoffs between the test application time and the required test area. Experimental results for the ITC'02 SOC Test Benchmarks show that the proposed TAM design algorithms increase the size of the solution space that is explored, which, in turn, will lower the test application time when compared to the existing solutions.

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Section: B Motivation and Summary Of Contributionsmentioning

confidence: 99%

Section: B Motivation and Summary Of Contributionsmentioning

confidence: 99%

Multifrequency TAM design for hierarchical SOCs

Nicolici²

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…In our experiments, we select NoWeights = 100 and normalWeight = 200 to limit the run time to a few seconds. Inside the inner loop (lines [8][9][10][11][12][13][14][15][16][17][18][19], the algorithm selects the shift frequency…”

Section: Heuristic For Wrapper Optimizationmentioning

confidence: 99%

“…Note that these distinct shift clock signals are generated inside the proposed core wrapper. Therefore, unlike in [16], we do not require the tester to shift data at multiple frequencies. Many low-and medium-end testers are not equipped with advanced port scalability features, which allow groups of channels to be driven at different data rates.…”

Section: Introductionmentioning

confidence: 99%

“…The above problems can be addressed by allowing distinct shift frequencies for scan chains in different clock domains, which can be in the range of tens to hundreds of MHz [16,20] based on the scan chain design and test power requirements. For example, if each clock domain can operate at a distinct shift frequency, lower TAT may be achieved under tight power constraints.…”

Section: Introductionmentioning

confidence: 99%

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Multi-frequency wrapper design and optimization for embedded cores under average power constraints

Nicolici

Chakrabarty

2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed method improves upon a recent wrapper design method that requires a common shift frequency for the scan elements in the different clock domains. We present an integer linear programming (ILP) model that can be used to minimize the testing time for small problem instances. We also present an efficient heuristic method that is applicable to large problem instances, and which yields the same (optimal) testing time as ILP for small problem instances. Compared to recent work on wrapper design using a single shift frequency, we obtain lower testing times and the reduction in testing time is especially significant under power constraints.

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Introduction to Advanced System-on-Chip Test Design and Optimization

Larsson¹

2005

Frontiers in Electronic Testing

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Efficient modular testing of SoCs using dual-speed TAM architectures

Abstract: The increasing complexity of system-on-chip (SOC)

Cited by 13 publications

References 13 publications

Multifrequency TAM design for hierarchical SOCs

Multifrequency TAM design for hierarchical SOCs

Multi-frequency wrapper design and optimization for embedded cores under average power constraints

Introduction to Advanced System-on-Chip Test Design and Optimization

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