Efficient modulo 2 ±1 squarers

Bakalis, D.; Vergos, H.T.; Spyrou, Alexandra

doi:10.1016/j.vlsi.2011.03.006

Cited by 14 publications

(3 citation statements)

References 26 publications

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“…1} [9][10][11][12] followed by a two-moduli MRC to include the fourth modulus. The hardware resource and conversion time requirements in terms of basic gates for the proposed reverse converters along with the converters for M1-M3 are also presented using unit-gate model [28] From table 4, it can be observed that for all the standard DRs, among the considered three-and four-moduli sets the design D12 is preferable regarding lower hardware resource requirement and the converter D13 needs least conversion time among all the converters. Among the converters D5-D10 for moduli set M1, the proposed converter D10 needs the lowest hardware resources for DR 8 and 16 bits whereas converter D5 is better for 24-, 32-, 48-and 64-bit DRs.…”

Section: Performance Evaluation and Comparisonmentioning

confidence: 99%

Novel RNS-to-binary converters for the three-moduli set {2m − 1, 2m, 2m + 1}

2019

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In this paper, Mixed Radix Conversion (MRC)-based Residue Number System (RNS)-to-binary converters for the three-moduli set {2m-1, 2m, 2m ? 1} are presented. The proposed reverse converters are evaluated and compared to reverse converters proposed earlier in literature using Chinese Remainder Theorem (CRT) and New CRT for this moduli set as well as two four-moduli sets {2 n-1, 2 n , 2 n ? 1, 2 n?1-1} and {2 n-1, 2 n , 2 n ? 1, 2 n?1 ? 1} regarding hardware requirement and conversion time.

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Section: Performance Evaluation and Comparisonmentioning

confidence: 99%

Novel RNS-to-binary converters for the three-moduli set {2m − 1, 2m, 2m + 1}

2019

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“…Arithmetic units perform their calculations on the k bits of each operand, while zeros are treated in a special way. As a result, the architectures for diminished-one modulo 2 k +1 addition, multiplication and squaring that have been presented [2], [8][9][10], [14], [27], [30] are more delay and/or area efficient than those for the normal encoding.…”

Section: Introductionmentioning

confidence: 99%

Reverse converters for RNSs with diminished-one encoded channels

2013

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The diminished-one encoding is often considered when representing the operands in the modulo 2 k +1 channels of a Residue Number System (RNS) since it can offer increased arithmetic processing speed. However, limited research is available on the design of residue-to-binary (reverse) converters for RNSs that use the diminished-one encoding in one or more channels. In this paper we introduce a simple methodology for designing such converters which can be applied to reverse converters based on the Chinese Remainder Theorem (CRT) or the New CRT-I method. Efficient converters for three moduli sets, covering different dynamic ranges, are also analytically presented. The proposed converters are shown to be area, delay and power efficient for several moduli sets.

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“…Modulo squaring is a special modulo multiplication operation where the multiplicand and the multiplier are identical. By manipulating the redundancy in the partial product matrix, efficient squarer circuits have been proposed in [Verg05], [Mura09a] where the operand bits are non-encoded and [Baka11] where both the multiplicand and multiplier bits are radix-4 Booth encoded. The high radix Booth encoding techniques suggested in this thesis can be extended to modulο 2 n −1, modulo 2 n and modulο 2 n +1 squarer circuits for improved area-delay-power metrics.…”

Section: Future Workmentioning

confidence: 99%

Novel modulo multipliers for moduli 2^n-1, 2^n and 2^n+1.

Muralidharan¹

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Long word-length integer multiplication is widely acknowledged as the bottleneck operation in public key cryptographic and signal processing algorithms. Residue Number System (RNS) has emerged as a promising alternative number representation for the design of faster and low power multipliers owing to its merit to distribute a long integer multiplication into several shorter and parallel modulo multiplications. To maximize the advantages offered by the RNS multiplier, judicious choice of moduli that constitute the RNS base and design of efficient modulo multipliers are imperative. In this thesis, special modulo 2 n −1, modulo 2 n and modulo 2 n +1 multipliers are studied. By manipulating the number theoretic properties of special moduli, 2 n −1, 2 n and 2 n +1, new low-power and low-area modulo multipliers are proposed. The modulo 2 n −1 multiplier is typically the non-critical datapath among all modulo multipliers in the RNS multiplier. This timing slack can be exploited to lower the area as well as power dissipation without compromising the performance of the RNS multiplier. A family of radix-8 Booth encoded modulo 2 n −1 multipliers with delay adaptable to match the RNS delay is proposed. The modulo 2 n −1 multiplier delay is made scalable by controlling the word-length k of the Ripple Carry Adder (RCA) that computes the necessary hard multiple, i.e., three time the multiplicand, of the radix-8 Booth encoding algorithm. The hard multiple and the simple multiples are consistently represented in partially-redundant biased forms. The compensation constant that negates the effect of the biased representation is proven to be a single constant n-bit word for all valid combinations of n and k. The adaptive delay of the modulo 2 n −1 multiplier is corroborated by synthesis results based on CMOS implementations. In an imbalanced word-length moduli set based RNS multiplier, where the critical modulo m multiplier delay is significantly greater than the non-critical modulo 2 n −1 multiplier delay, k = n and k = n/3 when n is not divisible by three and divisible by three, respectively, are recommended for maximal area-power savings. New radix-8 Booth encoded modulo 2 n −1 and modulo 2 n +1 multipliers that are equally applicable in critical and non-critical modulo channels as well as balanced and imbalanced viii word-length moduli sets are also proposed. Custom adders called Hard Multiple Generators (HMGs) that exclusively compute the required hard multiples of radix-8 Booth encoded modulo 2 n −1 and modulo 2 n +1 multiplications are designed. The parallel-prefix implementations of the proposed modulo 2 n −1 and modulo 2 n +1 HMGs employ the fewest number of prefix levels and hence are the fastest adders for this application. The moduloreduced partial products were generated with no accompanying bias in the proposed modulo 2 n −1 multiplier while the inevitable bias was succinctly expressed as three n-bit words in the proposed modulo 2 n +1 multiplier. The savings in area and power dissipation of the proposed radix-8 Booth ...

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Efficient modulo 2 ±1 squarers

Cited by 14 publications

References 26 publications

Novel RNS-to-binary converters for the three-moduli set {2m − 1, 2m, 2m + 1}

Novel RNS-to-binary converters for the three-moduli set {2m − 1, 2m, 2m + 1}

Reverse converters for RNSs with diminished-one encoded channels

Novel modulo multipliers for moduli 2^n-1, 2^n and 2^n+1.

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